1.3.1.1.1 DMA0—Host PC Memory to DDR3L/DDR4/LSRAM

PCIe DMA Engine0 performs continuous DMA from host PC memory to DDR3L/DDR4/LSRAM memories as described in the following steps:

1. The PolarFire_PCIe_GUI application sets the DMA controller through the PCIe link. This includes DMA source and destination, address and size.
2. DMA controller initiates a read transaction to the PCIe core.
3. The PCIe core sends the MRd TLP to the host PC.
4. The host PC returns a completion (CplD) TLP to the PCIe link.
5. This returned data is written to the DDR3L/DDR4/LSRAM memories using PCIe AXI initiator interface.
6. The DMA controller repeats this process (from steps 2 to 5) until the DMA size of data transfer is completed.
7. The DMA controller sends the MSI0 interrupt to the host PC, the driver on the host PC detects the interrupt, reads the DMA status and the number of clock cycles consumed to complete the DMA transaction to the PolarFire_PCIe_GUI application.