1.3.1.1.2 DMA1—DDR3L/DDR4/LSRAM to Host PC Memory

PCIe DMA Engine1 performs continuous DMA from DDR3L/DDR4/LSRAM memories to host PC memory as described in the following steps:

1. PolarFire_PCIe_GUI application sets up the DMA controller through the PCIe link. This includes DMA source and destination, address and size.
2. DMA controller initiates an AXI burst read transaction to read the data from DDR3L/DDR4/LSRAM memories.
3. The DMA controller initiates write transaction to PCIe core with the read data. The PCIe core sends a MWr TLP to the host PC.
4. The DMA controller repeats this process (steps 2 and 3) until the DMA size of data transfer is completed.
5. The DMA controller sends the MSI1 interrupt to the host PC. The driver on the host PC detects the interrupt, reads the DMA status and the number of clock cycles consumed to complete the DMA transaction to the PolarFire_PCIe_GUI application.