15.7.14 Peripheral Non-Secure Status - Bridge C
This register is loaded from UROW at boot.
Important: This register is only
available for SAM
L11 and has no effect
for SAM
L10.
Reading NONSEC register returns peripheral Security Attribution status:
| Value | Description |
|---|---|
| 0 | Peripheral is secured. |
| 1 | Peripheral is non-secured. |
| Name: | NONSECC |
| Offset: | 0x5C |
| Reset: | x initially determined from NVM User Row after reset |
| Property: | Write-Secure |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TRAM | OPAMP | CCL | TRNG | PTC | DAC | ||||
| Access | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | |||
| Reset | x | x | x | x | x | x |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADC | TC2 | TC1 | TC0 | SERCOM2 | SERCOM1 | SERCOM0 | EVSYS | ||
| Access | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | |
| Reset | x | x | x | x | x | x | x | x |