15.7.11 Peripheral Write Protection Status C

Reading the STATUSC register returns the peripheral write protection status:

Value Description
0 Peripheral is not write protected.
1 Peripheral is write protected.
Important: For SAM L11 Non-Secure accesses, read accesses (R*) are allowed only if the peripheral security attribution for the corresponding peripheral is set as Non-Secured in the NONSECx register.
Name: STATUSC
Offset: 0x3C
Reset: 0x000000
Property: Mix-Secure

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
   TRAMOPAMPCCLTRNGPTCDAC 
Access R/R*/RR/R*/RR/R*/RR/R*/RR/R*/RR/R*/R 
Reset 000000 
Bit 76543210 
 ADCTC2TC1TC0SERCOM2SERCOM1SERCOM0EVSYS 
Access R/R*/RR/R*/RR/R*/RR/R*/RR/R*/RR/R*/RR/R*/RR/R*/R 
Reset 00000000 

Bit 13 – TRAM Peripheral TRAM Write Protection Status

Bit 12 – OPAMP Peripheral OPAMP Write Protection Status

Bit 11 – CCL Peripheral CCL Write Protection Status

Bit 10 – TRNG Peripheral TRNG Write Protection Status

Bit 9 – PTC Peripheral PTC Write Protection Status

Bit 8 – DAC Peripheral DAC Write Protection Status

Bit 7 – ADC Peripheral ADC Write Protection Status

Bits 4, 5, 6 – TC Peripheral TCn Write Protection Status [n = 2..0]

Bits 1, 2, 3 – SERCOM Peripheral SERCOMn Write Protection Status [n = 2..0]

Bit 0 – EVSYS Peripheral EVSYS Write Protection Status