15.7.5 AHB Client Bus Interrupt Flag Status and Clear

This flag is cleared by writing a '1' to the flag.

This flag is set when an access error is detected by the CLIENT n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.

Name:	INTFLAGAHB
Offset:	0x10
Reset:	0x000000
Property:	Secure


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	BROM	HSRAMDSU	HSRAMDMAC	HSRAMCPU	APBC	APBB	APBA	FLASH
Access	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW
Reset	0	0	0	0	0	0	0	0

Bit 7 – BROM Interrupt Flag for Boot ROM

Bit 6 – HSRAMDSU Interrupt Flag for CLIENT HS SRAM Port 2 - DSU Access

Bit 5 – HSRAMDMAC Interrupt Flag for CLIENT HS SRAM Port 1 - DMAC Access

Bit 4 – HSRAMCPU Interrupt Flag for CLIENT HS SRAM Port 0 - CPU Access

Bit 3 – APBC Interrupt Flag for CLIENT AHB-APB Bridge C

Bit 2 – APBB Interrupt Flag for CLIENT AHB-APB Bridge B

Bit 1 – APBA Interrupt Flag for CLIENT AHB-APB Bridge A

Bit 0 – FLASH Interrupt Flag for CLIENT FLASH

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