15.7.4 Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENCLR).
Name: INTENSET
Offset: 0x09
Reset: 0x00
Property: PAC Write-Protection, Secure

Bit 76543210 
        ERR 
Access RW/-/RW 
Reset 0 

Bit 0 – ERR Peripheral Access Error Interrupt Enable

This bit indicates that the Peripheral Access Error Interrupt is enabled and an interrupt request will be generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set:

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Peripheral Access Error interrupt Enable bit and enables the corresponding interrupt request.

ValueDescription
0 Peripheral Access Error interrupt is disabled.
1 Peripheral Access Error interrupt is enabled.