15.7.12 Peripheral Non-Secure Status - Bridge A

This register is loaded from UROW at boot.

Important: This register is only available for SAM L11 and has no effect for SAM L10.

Reading NONSEC register returns peripheral security attribution status:

Value Description
0 Peripheral is secured.
1 Peripheral is non-secured.
Name: NONSECA
Offset: 0x54
Reset: x initially determined from NVM User Row after reset
Property: Write-Secure

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
   ACPORTFREQMEICRTCWDT 
Access R/R/RR/R/RR/R/RR/R/RR/R/RR/R/R 
Reset xxxxxx 
Bit 76543210 
 GCLKSUPCOSC32KCTRLOSCCTRLRSTCMCLKPMPAC 
Access R/R/RR/R/RR/R/RR/R/RR/R/RR/R/RR/R/RR/R/R 
Reset xxxxxxxx 

Bit 13 – AC Peripheral AC Non-Secure

Bit 12 – PORT Peripheral PORT Non-Secure

Bit 11 – FREQM Peripheral FREQM Non-Secure

Bit 10 – EIC Peripheral EIC Non-Secure

Bit 9 – RTC Peripheral RTC Non-Secure

Bit 8 – WDT Peripheral WDT Non-Secure

Bit 7 – GCLK Peripheral GCLK Non-Secure

Bit 6 – SUPC Peripheral SUPC Non-Secure

Bit 5 – OSC32KCTRL Peripheral OSC32KCTRL Non-Secure

Bit 4 – OSCCTRL Peripheral OSCCTRL Non-Secure

Bit 3 – RSTC Peripheral RSTC Non-Secure

Bit 2 – MCLK Peripheral MCLK Non-Secure

Bit 1 – PM Peripheral PM Non-Secure

Bit 0 – PAC Peripheral PAC Non-Secure

The PAC Peripheral is always secured.