15.5.31 SLRCONA

Slew Rate Control Register
Name: SLRCONA
Offset: 0xF0E

Bit 76543210 
 SLRA7SLRA6SLRA5SLRA4SLRA3SLRA2SLRA1SLRA0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 

Bits 0, 1, 2, 3, 4, 5, 6, 7 – SLRAn Slew Rate Control on Pins Rx<7:0>, respectively

ValueDescription
1 Port pin slew rate is limited
0 Port pin slews at maximum rate