11.2.1.1.2 Rising Edge Flip-Flop with Asynchronous Reset

The following examples infer a D flip-flop with an asynchronous reset. This flip-flop is a basic sequential cell in the Microchip antifuse architecture.

Figure 11-3. D Flip-Flop with Asynchronous Reset

VHDL

library IEEE;
use IEEE.std_logic_1164.all;
entity dff_async_rst is
port (data, clk, reset : in std_logic;
q : out std_logic);
end dff_async_rst;
architecture behav of dff_async_rst is
begin
process (clk, reset) begin
if (reset = '0') then
q <= '0';
elsif (clk'event and clk = '1') then
q <= data;
end if;
end process;
end behav;

Verilog

module dff_async_rst (data, clk, reset, q);
input data, clk, reset;
output q;
reg q;
always @(posedge clk or negedge reset)
if (~reset)
q = 1'b0;
else
q = data;
endmodule