11.2.1.1.3 Rising Edge Flip-Flop with Asynchronous Preset

The following examples infer a D flip-flop with an asynchronous preset. Refer to “Registers” for additional information about using preset flip-flops with the Microchip architecture.

Figure 11-4. D Flip-Flop with Asynchronous Preset

VHDL

library IEEE;
use IEEE.std_logic_1164.all;
entity dff_async_pre is
port (data, clk, preset : in std_logic;
q : out std_logic);
end dff_async_pre;
architecture behav of dff_async_pre is
begin
process (clk, preset) begin
if (preset = '0') then
q <= '1';
elsif (clk'event and clk = '1') then
q <= data;
end if;
end process;
end behav;

Verilog

module dff_async_pre (data, clk, preset, q);
input data, clk, preset;
output q;
reg q;
always @(posedge clk or negedge preset)
if (~preset)
q = 1'b1;
else
q = data;
endmodule