11.2.1.1.6 Rising Edge Flip-Flop with Synchronous Preset

The following examples infer a D flip-flop with a synchronous preset.

Figure 11-7. D Flip-Flop with Synchronous Preset

VHDL

library IEEE;
use IEEE.std_logic_1164.all;
entity dff_sync_pre is
port (data, clk, preset : in std_logic;
q : out std_logic);
end dff_sync_pre;
architecture behav of dff_sync_pre is
begin
process (clk) begin
if (clk'event and clk = '1') then
if (preset = '0') then
q <= '1';
else q <= data;
end if;
end if;
end process;
end behav;

Verilog

module dff_sync_pre (data, clk, preset, q);
input data, clk, preset;
output q;
reg q;
always @ (posedge clk)
if (~preset)
q = 1'b1;
else q = data;
endmodule