11.2.1.1.1 Rising Edge Flip-Flop

The following examples infer a D flip-flop without asynchronous or synchronous reset or preset. This flip-flop is a basic sequential cell in the Microchip antifuse architecture.

VHDL

library IEEE;
use IEEE.std_logic_1164.all;
entity dff is
port (data, clk : in std_logic;
q : out std_logic);
end dff;
architecture behav of dff is
begin
process (clk) begin
if (clk'event and clk = '1') then
q <= data;
end if;
end process;
end behav;

Verilog

module dff (data, clk, q);
input data, clk;
output q;
reg q;
always @(posedge clk)
q = data;
endmodule