11.2.1.1.4 Rising Edge Filp-Flop with Asynchronous Reset and Preset

The following examples infer a D flip-flop with an asynchronous reset and preset. Refer to “Registers” for additional information about using preset flip-flops with the Microchip architecture.

Figure 11-5. D Flip-Flop with Asynchronous Reset and Preset

VHDL

library IEEE;
use IEEE.std_logic_1164.all;
entity dff_async is
port (data, clk, reset, preset : in std_logic;
q : out std_logic);
end dff_async;
architecture behav of dff_async is
begin
process (clk, reset, preset) begin
if (reset = '0') then
q <= '0';
elsif (preset = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
q <= data;
end if;
end process;
end behav;

Verilog

module dff_async (reset, preset, data, q, clk);
input clk;
input reset, preset, data;
output q;
reg q;
always @ (posedge clk or negedge reset or posedge preset)
if (~reset)
q = 1'b0;
else if (preset)
q = 1'b1;
else q = data;
endmodule