6.13 Design Object Access Commands

None

IGLOO, ProASIC3, SmartFusion, Fusion, ProASIC PLUS, ProASIC, Axcelerator, eX, SX-A

None

set_max_delay -from [all_inputs] -to [get_clocks ck1]

None

-clock clock_name

Creates a collection of register cells or register pins in the specified clock domain.

-cells

Creates a collection of register cells. This is the default. This option cannot be used in combination with any other option.

-data_pins

Creates a collection of register data pins.

-clock_pins

Creates a collection of register clock pins.

-async_pins

Creates a collection of register asynchronous pins.

-output_pins

Creates a collection of register output pins.

IGLOO, ProASIC3, SmartFusion, Fusion, ProASIC PLUS, ProASIC, Axcelerator, eX, SX-A

This command creates either a collection of register cells (default) or register pins, whichever is specified. If you do not specify an option, this command creates a collection of register cells.

None

set_max_delay 2 -from [all_registers] -to [get_ports {out}] set_max_delay 3 –to [all_registers –async_pins] set_false_path –from [all_registers –clock clk150] set_multicycle_path –to [all_registers –clock c* -data_pins–clock_pins]

• None

-clock clock_name

Creates a collection of register cells or register pins in the specified clock domain.

-cells

Creates a collection of register cells. This is the default. This option cannot be used in combination with any other option.

-data_pins

Creates a collection of register data pins.

-clock_pins

Creates a collection of register clock pins.

-async_pins

Creates a collection of register asynchronous pins.

-output_pins

Creates a collection of register output pins.

IGLOO, ProASIC3, SmartFusion, Fusion, ProASIC PLUS, ProASIC, Axcelerator, eX, SX-A

This command creates either a collection of register cells (default) or register pins, whichever is specified. If you do not specify an option, this command creates a collection of register cells.

None

set_max_delay 2 -from [all_registers] -to [get_ports {out}] set_max_delay 3 –to [all_registers –async_pins] set_false_path –from [all_registers –clock clk150] set_multicycle_path –to [all_registers –clock c* -data_pins–clock_pins]

None

pattern

Specifies the pattern to match the instances to return. For example, "get_cells U18*" returns all instances starting with the characters "U18", where “*” is a wildcard that represents any character string.

IGLOO, ProASIC3, SmartFusion, Fusion, Axcelerator, RTAX-S, eX, and SX-A

This command returns a collection of instances matching the pattern you specify. You can only use this command as part of a –from, -to, or –through argument for the following constraint exceptions: set_max delay, set_multicycle_path, and set_false_path design constraints.

None

set_max_delay 2 -from [get_cells {reg*}] -to [get_ports {out}] set_false_path –through [get_cells {Rblock/muxA}]

None

pattern

Specifies the pattern to match to the Timer or SmartTime on which a clock constraint has been set.

IGLOO, ProASIC3, SmartFusion, Fusion, Axcelerator, RTAX-S, eX, and SX-A

• If this command is used as a –from argument in maximum delay (set_max_path_delay), false path (set_false_path), and multicycle constraints (set_multicycle_path), the clock pins of all the registers related to this clock are used as path start points.
• If this command is used as a –to argument in maximum delay (set_max_path_delay), false path (set_false_path), and multicycle constraints (set_multicycle_path), the synchronous pins of all the registers related to this clock are used as path endpoints.

None

set_max_delay -from [get_ports datal] -to \ [get_clocks ck1]

None

pattern

Specifies the pattern to match the pins.

IGLOO, ProASIC3, SmartFusion, Fusion, Axcelerator, RTAX-S, eX, and SX-A

None

create_clock -period 10 [get_pins clock_gen/reg2:Q]

None

pattern

Specifies the pattern to match the names of the nets to return. For example, "get_nets N_255*" returns all nets starting with the characters "N_255", where “*” is a wildcard that represents any character string.

IGLOO, ProASIC3, SmartFusion, Fusion, Axcelerator, RTAX-S, eX, and SX-A

This command returns a collection of nets matching the pattern you specify. You can only use this command as source objects in create clock (create_clock) or create generated clock (create_generated_clock) constraints and as - through arguments in set false path (set_false_path), set minimum delay (set_min_delay), set maximum delay (set_max_delay), and set multicycle path (set_multicycle_path) constraints.

None

set_max_delay 2 -from [get_ports RDATA1] -through [get_nets {net_chkp1 net_chkqi}] set_false_path –through [get_nets {Tblk/rm/n*}]

create_clcok -name mainCLK -per 2.5 [get_nets {cknet}]

None

pattern

Specifies the pattern to match the ports. This is equivalent to the macros $in()[<pattern>] when used as –from argument and $out()[<pattern>] when used as –to argument or $ports()[<pattern>] when used as a –through argument.

IGLOO, ProASIC3, SmartFusion, Fusion, Axcelerator, RTAX-S, eX, and SX-A

None

create_clock -period 10[get_ports CK1]

None