6.9 Constraints by Name: Timing

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

(*) Supported for analysis only.

Use this constraint to create a clock constraint at a specific source and define its waveform. The static timing analysis tool uses this information to propagate the waveform across the clock network to the clock pins of all sequential elements driven by the defined clock source. The clock information is also used to compute the slacks in the specified clock domain, display setup and hold violations, and drive optimization tools such as place-and-route.

You can use one or more of the following methods to enter clock constraints:

• SDC - create_clock
• DCF – global_clocks
• Timer - Clocks tab
• SmartTime - Specifying Clock Constraint

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

(*) Supported for analysis only

Use this constraint to create an internally generated clock constraint, such as clock dividers and PLL. The generated clock is defined in terms of multiplication and/or division factors with respect to a reference clock pin. When the reference clock pin changes, the generated clock is updated automatically.

You can use one or more of the following methods to enter clock constraints:

• SDC – create_generated_clock
• SmartTime - Specifying Generated Clock Constraint

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

(*) Supported for analysis only.

Use this constraint to remove the timing uncertainty between two clock waveforms within SmartTime.

You can remove clock uncertainty constraints in an SDC file, which you can either create yourself or generate with Synthesis tools, at the same time you import the netlist. Alternatively, you can remove clock uncertainty using the GUI tools in the Designer software.

You can use one or more of the following commands or GUI tools to remove clock uncertainty:

• SDC – remove_clock_uncertainty
• SmartTime - Specifying Clock-to-Clock Uncertainty Constraint

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

(*) Supported for analysis only.

Use this constraint to define the delay between an external clock source and the definition pin of a clock within SmartTime.

You can set clock latency constraints in an SDC file, which you can either create yourself or generate with Synthesis tools, at the same time you import the netlist. Alternatively, you can set clock latency using the GUI tools in the Designer software when you implement your design.

You can use one or more of the following commands or GUI tools to set clock latency:

• SDC – set_clock_latency
• SmartTime - Specifying Clock Source Latency

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

(*) Supported for analysis only.

Use this constraint to define the timing uncertainty between two clock waveforms or maximum skew within SmartTime.

You can set clock uncertainty constraints in an SDC file, which you can either create yourself or generate with Synthesis tools, at the same time you import the netlist. Alternatively, you can set clock uncertainty using the GUI tools in the Designer software when you implement your design.

You can use one or more of the following commands or GUI tools to set clock uncertainty:

• SDC – set_clock_uncertainty
• SmartTime - Specifying Clock-to-Clock Uncertainty Constraint

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

(*) Supported for analysis only.

Use this constraint disable the timing arc in the specified ports on a path.

You can disable the timing arc in an SDC file, which you can either create yourself or generate with Synthesis tools, at the same time you import the netlist. Alternatively, you can disable the timing arc using the GUI tools in the Designer software when you implement your design.

You can use one or more of the following commands or GUI tools to set maximum delay exception constraints:

• SDC – set_disable_timing
• SmartTime – Specifying Disable Timing Constraint

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

(*) Supported for analysis only.

(***) Only the -through option is supported for layout.

Use this constraint to identify paths in the design that should be disregarded during timing analysis and timing optimization.

By definition, false paths are paths that cannot be sensitized under any input vector pair. Therefore, including false paths in timing calculation may lead to unrealistic results. For accurate static timing analysis, it is important to identify the false paths.

You can set false paths constraints in an SDC file, which you can either create yourself or generate with Synthesis tools, at the same time you import the netlist. Alternatively, you can set false paths using the GUI tools in the Designer software when you implement your design.

You can use one or more of the following commands or GUI tools to set false paths:

• SDC – set_false_path
• DCF -global_stops
• Timer - Breaks Tab
• SmartTime - Specifying False Path Constraint

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

(*) Supported for analysis only.

(**) Supported for layout only.

Use this constraint to define the arrival time relative to a clock.

You can use one or more of the following methods to set input delay constraint:

• SDC – set_input_delay
• SmartTime - Specifying Input Delay Constraint

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to set the capacitance to a specified value on a specified port.

Delay on a given path depends on the load at the output pin of the device. For an accurate static timing analysis of a given design, it is important to set the load on the port which can be taken into account for delay calculations.

You can use one or more of the following commands or GUI tools to set the load on a port:

• SDC – set_load
• DCF – pin_loads
• I/O Attribute Editor – Editing I/O Attributes
• PinEditor (non–MVN) – Specifying Capacitance
• SmartTime Constraints Editor GUI – Changing Output Port Capacitance

You can also set the output load using the pin_assign command in a Tcl script.

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

(*) Supported for analysis only.

(**) the -through option is not supported for layout.

Use this constraint to set the maximum delay exception between the specified ports on a path.

You can set maximum delay exception in an SDC file, which you can either create yourself or generate with Synthesis tools, at the same time you import the netlist. Alternatively, you can set maximum delay exceptions using the GUI tools in the Designer software when you implement your design.

You can use one or more of the following commands or GUI tools to set maximum delay exception constraints:

• SDC – set_max_delay
• DCF – pin_loads, max_delays
• Timer – Paths Tab
• SmartTime – Specifying Maximum Delay Constraint

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

(*) Supported for analysis only.

(**) the -through option is not supported for layout.

Use this constraint to set the minimum delay exception between the specified ports on a path.

You can set minimum delay exception in an SDC file, which you can either create yourself or generate with Synthesis tools, at the same time you import the netlist. Alternatively, you can set minimum delay exceptions using the GUI tools in the Designer software when you implement your design.

You can use one or more of the following commands or GUI tools to set maximum delay exception constraints:

• SDC – set_min_delay
• SmartTime – Specifying minimum delay constraint

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

(*) Supported for analysis only.

Use this constraint to identify paths in the design that take multiple clock cycles.

You can set multicycle path constraints in an SDC file, which you can either create yourself or generate with Synthesis tools, at the same time you import the netlist. Alternatively, you can set multicycle paths using the GUI tools in the Designer software when you implement your design.

You can use one or more of the following commands or GUI tools to set multicycle paths constraints:

• SDC – set_multicycle_path
• SmartTime – Specifying Input Delay Constraint

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

(*) Supported for analysis only.

Use this constraint to set the output delay of an output relative to a clock.

You can use one or more of the following methods to set output delay constraints:

• SDC – set_output_delay
• SmartTime – Specifying Output Delay Constraint