6.2 Families Supported

6.2.1 Constraint Support by Family

Use the Constraint Family Support table to see which constraints you can use for your device family. Click the name of a constraint in the table for more information about it.

Table 6-1. Constraint Support by Family
IGLOOSmartFusion and FusionProASIC3ProASIC PlusProASICAxceleratoreXSX-ASXMXDXACT1ACt2/1200XLACT3
Timing
Create ClockXXXXXXXXXXXXXX
Create Generated ClockXXXXXXXX
Remove Clock UncertainityXXXXXXXX
Set Clock LatencyXXXXXXXX
Set Clock Uncertainty ConstraintXXXXXXXX
Set Disable Timing ConstraintXXXX (including RTAX-S)XX
Set False PathXXXXXXXXXXXXXX
Set Input DelayXXXXX
Set Load on Output PortXXXXXXXX
Set Maximum DelayXXXXXXXXXXXXXX
Set Minimum DelayXXXXXXXXXXXXXX
Set Multicycle PathXXXXX
Set Output DelayXXXXX
Physical Placement

-Clocks

Assign Net to Global ClockXXXXX
Assign Net to Local ClockXXXXXX
Assign Net to Quadrant ClockXXX

-Region

Assign Macro to RegionXXXXXX
Assign Net to RegionXXXXXX
Create RegionXXXXXX
Delete RegionsXXXXXX
Move RegionXXXXXX
Unassign Macro(s) Driven by Net from RegionXXXXXX
Unassign Macro from RegionXXXXXX

-I/Os

Assign I/O to pinXXXXXXXXXXXXXX
Assign I/O Macro to LocationXXXXXX
Configure I/O BankXXXX
Reset Attributes on an I/O to Default SettingsXXXXXX
Reset an I/O Bank to Default SettingsXXXX
Reserve PinsXXXXXXX
Unreserve PinsXXXXXXX
Unassign I/O Macro from LocationXXXXXX

-Block

Move BlockXXXX
Set Port BlockXXXX
Set Block OptionsXXXX

-Nets

Assign Net to Global ClockXXXXX
Assign Net to Local ClockXXXXXX
Assign Net to Quadrant ClockXXX
Assign Net to RegionXXXXXX
Reset Net's Criticality to Default LevelX
Set Net's CriticalityX
Unassign Macro(s) Driven by Net from RegionXXXXX

Netlist Optimization

Delete Buffer TreeXXX
Demote Global Net to Regular NetXXXXX
Promote Regular Net to Global NetXXXXX
Restore Buffer TreeXXXXX
Set PreserveXXXX

6.2.2 Constraint Entry

Use the Constraint Entry table to see which tools and file formats you can use to enter constraints for your device family.

Click the name of a constraint, a constraint entry tool, file format type, editor, or checkmark in the table for more information about that item.

Table 6-2. Constraint Entry by Tool and File Format
Constraint Entry by Tool and File Format
ConstraintSDCGDCPDCPINDCFChipPlannerI/O Attribute EditorPinEditorSmartTime, TimerCompile Options
Timing
Create ClockXXX
Create Generated ClockXX
Remove Clock UncertainityXX
Set Clock LatencyXX
Set Clock Uncertainty ConstraintXX
Set Disable Timing ConstraintXX
Set False PathXXX
Set Input DelayXX
Set Load on Output PortXXXXX
Set Maximum DelayXXX
Set Minimum DelayXX
Set Multicycle PathXX
Set Output DelayXX
Physical Placement
-Clocks
Assign Net to Global ClockXX
Assign Net to Local ClockXXX
Assign Net to Quadrant ClockXX
-Regions
Assign Macro to RegionXX
Assign Net to RegionXXX
Create RegionXXX
Delete RegionsXX
Move RegionXX
Unassign Macro(s) Driven by Net from RegionXX
Unassign Macro from RegionXX
-I/Os
Assign I/O to pinXXXXXX
Assign I/O Macro to LocationXXX
Configure I/O BankXXX
Reset Attributes on an I/O to Default SettingsXXX
Reset an I/O Bank to Default SettingsXXX
Reserve pinsXXX
Unreserve PinsXXX
Unassign I/O Macro from LocationXX
-Blocks
Move BlockX
Set Port BlockXX
Set Block OptionsXX
-Nets
Assign Net to Global ClockXX
Assign Net to Local ClockXXX
Assign Net to Quadrant ClockXX
Assign Net to RegionXXX
Reset Net's Criticality to Default LevelX
Set Net's CriticalityXX
Unassign Macro(s) Driven by Net from RegionXX
Netlist Optimization
Delete Buffer TreeXXX
Demote Global Net to Regular NetXXX
Promote Regular Net to Global NetXXX
Restore Buffer TreeXX
Set PreserveX

6.2.3 Constraint File Format by Family

Use the File Format by Family table to see which file formats apply to each type of constraint and each device family.

Table 6-3. Constraint File Format by Family
FamilyTimingPhysical PlacementNetlist Optimization
SDCDCFPDCPINGCFPDCGCF
IGLOOXX
SmartFusion / FusionXXX
ProASIC3XX
ProASIC PLUSXXX
ProASICXXX
AxceleratorXXX
eXXXX
SX-AXXX
SXXX
MXXX
DXXX
ACT3XX
ACT2/1200XLXX
ACT1XX

SDC – Synopsys Design Constraints

PDC – Physical Design Constraints for IGLOO, ProASIC3, SmartFusion, Fusion, and Axcelerator

GCF – Design Constraints Format for ProASIC PLUS and ProASIC

DCF – Microchip Design Constraints Format PIN – Pin location constraints