6.12 Constraints by File Format - SDC Command Reference

The following example shows syntax for the create_clock command and a sample command:

create_clock -period period_value [-waveform edge_list] source

create_clock –period 7 –waveform {2 4}{CLK1}

You can use the following wildcard characters in names used in the SDC commands:

The matching function requires that you add a backslash (\) before each slash in the pin names in case the slash does not denote the hierarchy in your design.

Square brackets ([ ]) are part of the command syntax to access ports, pins and clocks. In cases where these netlist objects names themselves contain square brackets (for example, buses), you must either enclose the names with curly brackets ({}) or precede the open and closed square brackets ([ ]) characters with a backslash (\). If you do not do this, the tool displays an error message.

For example:

create_clock -period 3 clk\[0\]

set_max_delay 1.5 -from [get_pins ff1\[5\]:CLK] -to [get_clocks {clk[0]}]

Although not necessary, Microchip recommends the use of curly brackets around the names, as shown in the following example:

set_false_path –from {data1} –to [get_pins {reg1:D}]

In any case, the use of the curly bracket is mandatory when you have to provide more than one name. For example:

set_false_path –from {data3 data4} –to [get_pins {reg2:D reg5:D}]

If a command needs to be split on multiple lines, each line except the last must end with a backslash (\) character as shown in the following example:

set_multicycle_path 2 –from \ [get_pins {reg1*}] \

-to {reg2:D}

-name name

Specifies the name of the clock constraint. This parameter is required for virtual clocks when no clock source is provided.

-period period_value

Specifies the clock period in nanoseconds. The value you specify is the minimum time over which the clock waveform repeats. The period_value must be greater than zero.

-waveform edge_list

Specifies the rise and fall times of the clock waveform in ns over a complete clock period. There must be exactly two transitions in the list, a rising transition followed by a falling transition. You can define a clock starting with a falling edge by providing an edge list where fall time is less than rise time. If you do not specify -waveform option, the tool creates a default waveform, with a rising edge at instant 0.0 ns and a falling edge at instant (period_value/2)ns.

source

Specifies the source of the clock constraint. The source can be ports or pins in the design. If you specify a clock constraint on a pin that already has a clock, the new clock replaces the existing one. Only one source is accepted. Wildcards are accepted as long as the resolution shows one port or pin.

IGLOO, ProASIC3, ProASIC PLUS, Axcelerator, ProASIC (for analysis), eX, SX-A

Creates a clock in the current design at the declared source and defines its period and waveform. The static timing analysis tool uses this information to propagate the waveform across the clock network to the clock pins of all sequential elements driven by this clock source.

The clock information is also used to compute the slacks in the specified clock domain that drive optimization tools such as place-and-route.

• None

The following example creates two clocks on ports CK1 and CK2 with a period of 6, a rising edge at 0, and a falling edge at 3:

create_clock -name {my_user_clock} -period 6 CK1

create_clock -name {my_other_user_clock} –period 6 –waveform {0 3} {CK2}

The following example creates a clock on port CK3 with a period of 7, a rising edge at 2, and a falling edge at 4:

create_clock –period 7 –waveform {2 4} [get_ports {CK3}]

• The -waveform in SDC accepts waveforms with multiple edges within a period. In Microchip design implementation, only two waveforms are accepted.
• SDC accepts defining a clock on many sources using a single command. In Microchip design implementation, only one source is accepted.
• The source argument in SDC create_clock command is optional. This is in conjunction with the -name argument in SDC to support the concept of virtual clocks. In Microchip implementation, source is a mandatory argument as -name and virtual clocks concept is not supported.

• The -domain argument in the SDC create_clock command is not supported.

-name name

Specifies the name of the clock constraint. This parameter is required for virtual clocks when no clock source is provided.

-source reference_pin

Specifies the reference pin in the design from which the clock waveform is to be derived.

-divide_bydivide_factor

Specifies the frequency division factor. For instance if the divide_factor is equal to 2, the generated clock period is twice the reference clock period.

-multiply_by multiply_factor

Specifies the frequency multiplication factor. For instance if the multiply_factor is equal to 2, the generated clock period is half the reference clock period.

-invert

Specifies that the generated clock waveform is inverted with respect to the reference clock.

source

Specifies the source of the clock constraint on internal pins of the design. If you specify a clock constraint on a pin that already has a clock, the new clock replaces the existing clock. Only one source is accepted. Wildcards are accepted as long as the resolution shows one pin.

IGLOO, ProASIC3,SmartFusion, Fusion, ProASIC PLUS, ProASIC (for analysis), Axcelerator, eX, SX-A

Creates a generated clock in the current design at a declared source by defining its frequency with respect to the frequency at the reference pin. The static timing analysis tool uses this information to compute and propagate its waveform across the clock network to the clock pins of all sequential elements driven by this source.

The generated clock information is also used to compute the slacks in the specified clock domain that drive optimization tools such as place-and-route.

None

The following example creates a generated clock on pin U1/reg1:Q with a period twice as long as the period at the reference port CLK.

create_generated_clock -name {my_user_clock} –divide_by 2 –source [get_ports {CLK}] U1/reg1:Q

The following example creates a generated clock at the primary output of myPLL with a period ¾ of the period at the reference pin clk.

create_generated_clock –divide_by 3 –multiply_by 4 -source clk [get_pins {myPLL:CLK1}]

• SDC accepts either –multiply_by or –divide_by option. In Microchip design implementation, both are accepted to accurately model the PLL behavior.
• SDC accepts defining a generated clock on many sources using a single command. In Microchip design implementation, only one source is accepted.
• The -duty_cycle ,-edges and –edge_shift options in the SDC create_generated_clock command are not supported in Microchip design implementation.

-from

Specifies that the clock-to-clock uncertainty applies to both rising and falling edges of the source clock list. You can specify only one of the -from, -rise_from, or -fall_from arguments for the constraint to be valid.

-rise_from

Specifies that the clock-to-clock uncertainty applies only to rising edges of the source clock list. You can specify only one of the -from, -rise_from, or -fall_from arguments for the constraint to be valid.

-fall_from

Specifies that the clock-to-clock uncertainty applies only to falling edges of the source clock list. You can specify only one of the -from, -rise_from, or -fall_from arguments for the constraint to be valid.

from_clock_list

Specifies the list of clock names as the uncertainty source.

-to

Specifies that the clock-to-clock uncertainty applies to both rising and falling edges of the destination clock list. You can specify only one of the -to, -rise_to , or -fall_to arguments for the constraint to be valid.

-rise_to

Specifies that the clock-to-clock uncertainty applies only to rising edges of the destination clock list. You can specify only one of the -to, -rise_to , or -fall_to arguments for the constraint to be valid.

-fall_to

Specifies that the clock-to-clock uncertainty applies only to falling edges of the destination clock list. You can specify only one of the -to, -rise_to , or -fall_to arguments for the constraint to be valid.

to_clock_list

Specifies the list of clock names as the uncertainty destination.

-setup

Specifies that the uncertainty applies only to setup checks. If none or both -setup and -hold are present, the uncertainty applies to both setup and hold checks.

-hold

Specifies that the uncertainty applies only to hold checks. If none or both -setup and -hold are present, the uncertainty applies to both setup and hold checks.

-id constraint_ID

Specifies the ID of the clock constraint to remove from the current scenario. You must specify either the exact parameters to set the constraint or its constraint ID.

IGLOO, ProASIC3, SmartFusion, Fusion, ProASIC PLUS, ProASIC (for analysis), Axcelerator, RTAX-S, eX (for analysis), SX-A (for analysis)

Removes a clock-to-clock uncertainty from the specified clock in the current scenario. If the specified arguments do not match clocks with an uncertainty constraint in the current scenario, or if the specified ID does not refer to a clock-to-clock uncertainty constraint, this command fails.

Do not specify both the exact arguments and the ID.

None

remove_clock_uncertainty -from Clk1 -to Clk2

remove_clock_uncertainty -from Clk1 -fall_to { Clk2 Clk3 } -setup

remove_clock_uncertainty 4.3 -fall_from { Clk1 Clk2 } -rise_to *

remove_clock_uncertainty 0.1 -rise_from [ get_clocks { Clk1 Clk2 } ] -fall_to { Clk3 Clk4 } -setup

remove_clock_uncertainty 5 -rise_from Clk1 -to [ get_clocks {*} ]

remove_clock_uncertainty -id $clockId

-source

Specifies a clock source latency on a clock pin.

-rise

Specifies the edge for which this constraint will apply. If neither or both rise are passed, the same latency is applied to both edges.

-fall

Specifies the edge for which this constraint will apply. If neither or both rise are passed, the same latency is applied to both edges.

-invert

Specifies that the generated clock waveform is inverted with respect to the reference clock.

-late

Optional. Specifies that the latency is late bound on the latency. The appropriate bound is used to provide the most pessimistic timing scenario. However, if the value of "-late" is less than the value of "-early", optimistic timing takes place which could result in incorrect analysis. If neither or both "-early" and "-late" are provided, the same latency is used for both bounds, which results in the latency having no effect for single clock domain setup and hold checks.

-early

Optional. Specifies that the latency is early bound on the latency. The appropriate bound is used to provide the most pessimistic timing scenario. However, if the value of "-late" is less than the value of "-early", optimistic timing takes place which could result in incorrect analysis. If neither or both "-early" and "-late" are provided, the same latency is used for both bounds, which results in the latency having no effect for single clock domain setup and hold checks.

delay

Specifies the latency value for the constraint.

clock

Specifies the clock to which the constraint is applied. This clock must be constrained.

IGLOO, ProASIC3, SmartFusion, Fusion, ProASIC PLUS, Axcelerator, ProASIC (for analysis), eX, SX-A

Clock source latency defines the delay between an external clock source and the definition pin of a clock within SmartTime. It behaves much like an input delay constraint. You can specify both an "early" delay and a"late" delay for this latency, providing an uncertainty which SmartTime propagates through its calculations. Rising and falling edges of the same clock can have different latencies. If only one value is provided for the clock source latency, it is taken as the exact latency value, for both rising and falling edges.

None

The following example sets an early clock source latency of 0.4 on the rising edge of main_clock. It also sets a clock source latency of 1.2, for both the early and late values of the falling edge of main_clock. The late value for the clock source latency for the falling edge of main_clock remains undefined.

set_clock_latency –source –rise –early 0.4 { main_clock } set_clock_latency –source –fall 1.2 { main_clock }

SDC accepts a list of clocks to -set_clock_latency. In Microchip design implementation, only one clock pin can have its source latency specified per command.

uncertainty

Specifies the time in nanoseconds that represents the amount of variation between two clock edges. The value must be a positive floating point number.

-from

Specifies that the clock-to-clock uncertainty applies to both rising and falling edges of the source clock list. You can specify only one of the -from, -rise_from, or -fall_from arguments for the constraint to be valid. This option is the default.

-rise_from

Specifies that the clock-to-clock uncertainty applies only to rising edges of the source clock list. You can specify only one of the -from, -rise_from, or -fall_from arguments for the constraint to be valid.

-fall_from

Specifies that the clock-to-clock uncertainty applies only to falling edges of the source clock list. You can specify only one of the -from, -rise_from, or -fall_from arguments for the constraint to be valid.

from_clock_list

Specifies the list of clock names as the uncertainty source.

-to

Specifies that the clock-to-clock uncertainty applies to both rising and falling edges of the destination clock list. You can specify only one of the -to, -rise_to , or -fall_to arguments for the constraint to be valid.

-rise_to

Specifies that the clock-to-clock uncertainty applies only to rising edges of the destination clock list. You can specify only one of the -to, -rise_to , or -fall_to arguments for the constraint to be valid.

-fall_to

Specifies that the clock-to-clock uncertainty applies only to falling edges of the destination clock list. You can specify only one of the -to, -rise_to , or -fall_to arguments for the constraint to be valid.

to_clock_list

Specifies the list of clock names as the uncertainty destination.

-setup

Specifies that the uncertainty applies only to setup checks. If you do not specify either option (-setup or -hold ) or if you specify both options, the uncertainty applies to both setup and hold checks.

-hold

Specifies that the uncertainty applies only to hold checks. If you do not specify either option (-setup or -hold ) or if you specify both options, the uncertainty applies to both setup and hold checks.

IGLOO, ProASIC3, SmartFusion, Fusion, ProASIC PLUS, Axcelerator, ProASIC (for analysis), eX, SX-A

Clock uncertainty defines the timing between an two clock waveforms or maximum clock skew.

Both setup and hold checks must account for clock skew. However, for setup check, SmartTime looks for the smallest skew. This skew is computed by using the maximum insertion delay to the launching sequential component and the shortest insertion delay to the receiving component.

For hold check, SmartTime looks for the largest skew. This skew is computed by using the shortest insertion delay to the launching sequential component and the largest insertion delay to the receiving component. SmartTime makes this distinction automatically.

None

The following example defines two clocks and sets the uncertainty constraints, which analyzes the inter-clock domain between clk1 and clk2.

create_clock –period 10 clk1

create_generated_clock –name clk2 -source clk1 -multiply_by 2 sclk1 set_clock_uncertainty 0.4 -rise_from clk1 -rise_to clk2

• SDC accepts a list of clocks to -set_clock_uncertainty.

-from from_port

Specifies the starting port.

-to to_port

Specifies the ending port.

cell_name

Specifies the name of the cell in which timing arcs will be disabled.

IGLOO, ProASIC3, SmartFusion, Fusion, Axcelerator, and RTAX-S

This command disables the timing arcs in the specified cell, and returns the ID of the created constraint if the command succeeded. The –from and –to arguments must either both be present or both omitted for the constraint to be valid.

The following example disables the arc between a2:A and a2:Y.

set_disable_timing -from port1 -to port2 cellname

This command ensures that the arc is disabled within a cell instead of between cells.

None

-from from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-through through_list

Specifies a list of pins, ports, cells, or nets through which the disabled paths must pass.

-to to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

IGLOO, ProASIC3, SmartFusion, Fusion, ProASIC PLUS, Axcelerator, ProASIC (for analysis), eX (-through option), SX-A (-through option)

The set_false_path command identifies specific timing paths as being false. The false timing paths are paths that do not propagate logic level changes. This constraint removes timing requirements on these false paths so that they are not considered during the timing analysis. The path starting points are the input ports or register clock pins, and the path ending points are the register data pins or output ports. This constraint disables setup and hold checking for the specified paths.

The false path information always takes precedence over multiple cycle path information and overrides maximum delay constraints. If more than one object is specified within one -through option, the path can pass through any objects.

The following example specifies all paths from clock pins of the registers in clock domain clk1 to data pins of a specific register in clock domain clk2 as false paths:

set_false_path –from [get_clocks {clk1}] –to reg_2:D

The following example specifies all paths through the pin U0/U1:Y to be false:

set_false_path -through U0/U1:Y

SDC accepts multiple -through options in a single constraint to specify paths that traverse multiple points in the design. In Microchip design implementation, only one –through option is accepted.

delay_value

Specifies the arrival time in nanoseconds that represents the amount of time for which the signal is available at the specified input after a clock edge.

-clock clock_ref

Specifies the clock reference to which the specified input delay is related. This is a mandatory argument. If you do not specify -max or -min options, the tool assumes the maximum and minimum input delays to be equal.

-max

Specifies that delay_value refers to the longest path arriving at the specified input. If you do not specify -max or -min options, the tool assumes maximum and minimum input delays to be equal.

-min

Specifies that delay_value refers to the shortest path arriving at the specified input. If you do not specify -max or - min options, the tool assumes maximum and minimum input delays to be equal.

-clock_fall

Specifies that the delay is relative to the falling edge of the clock reference. The default is the rising edge.

input_list

Provides a list of input ports in the current design to which delay_value is assigned. If you need to specify more than one object, enclose the objects in braces ({}).

IGLOO, ProASIC3, SmartFusion, Fusion, ProASIC PLUS, ProASIC (for analysis),Axcelerator, eX (for analysis), SX-A (for analysis)

The set_input_delay command sets input path delays on input ports relative to a clock edge. This usually represents a combinational path delay from the clock pin of a register external to the current design. For in/out (bidirectional) ports, you can specify the path delays for both input and output modes. The tool adds input delay to path delay for paths starting at primary inputs.

A clock is a singleton that represents the name of a defined clock constraint. This can be:

• a single port name used as source for a clock constraint
• a single pin name used as source for a clock constraint; for instance reg1:CLK. This name can be hierarchical (for instance toplevel/block1/reg2:CLK)
• an object accessor that will refer to one clock: [get_clocks {clk}]

The following example sets an input delay of 1.2ns for port data1 relative to the rising edge of CLK1:

set_input_delay 1.2 -clock [get_clocks CLK1] [get_ports data1]

The following example sets a different maximum and minimum input delay for port IN1 relative to the falling edge of CLK2:

set_input_delay 1.0 -clock_fall -clock CLK2 –min {IN1} set_input_delay 1.4 -clock_fall -clock CLK2 –max {IN1}

In SDC, the -clock is an optional argument that allows you to set input delay for combinational designs. Microchip implementation currently requires this argument.

capacitance

Specifies the capacitance value that must be set on the specified ports.

port_list

Specifies a list of ports in the current design on which the capacitance is to be set.

IGLOO, ProASIC3, SmartFusion, Fusion, Axcelerator, RTAX-S, eX, and SX-A

The load constraint enables the Designer software to account for external capacitance at a specified port. You cannot set load constraint on the nets. When you specify this constraint on the output ports, it impacts the delay calculation on the specified ports.

The following examples show how to set output capacitance on different output ports:

set_load 35 out_p

set_load 40 {O1 02}

set_load 25 [get_ports out]

In SDC, you can use the set_load command to specify capacitance value on nets. Microchip implementation only supports output ports.

delay_value

Specifies a floating point number in nanoseconds that represents the required maximum delay value for specified paths.

• If the path starting point is on a sequential device, the tool includes clock skew in the computed delay.
• If the path starting point has an input delay specified, the tool adds that delay value to the path delay.
• If the path ending point is on a sequential device, the tool includes clock skew and library setup time in the computed delay.
• If the ending point has an output delay specified, the tool adds that delay to the path delay.

-from from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-to to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

IGLOO, ProASIC3, SmartFusion, Fusion, ProASIC PLUS, ProASIC (for analysis), Axcelerator, eX (-through option), SX-A (-through option)

This command specifies the required maximum delay for timing paths in the current design. The path length for any startpoint in from_list to any endpoint in to_list must be less than delay_value.

The tool automatically derives the individual maximum delay targets from clock waveforms and port input or output delays. For more information, refer to the create_clock, set_input_delay, and set_output_delay commands.

The maximum delay constraint is a timing exception. This constraint overrides the default single cycle timing relationship for one or more timing paths. This constraint also overrides a multicycle path constraint.

The following example sets a maximum delay by constraining all paths from ff1a:CLK or ff1b:CLK to ff2e:D with a delay less than 5 ns:

set_max_delay 5 -from {ff1a:CLK ff1b:CLK} -to {ff2e:D}

The following example sets a maximum delay by constraining all paths to output ports whose names start by “out” with a delay less than 3.8 ns:

set_max_delay 3.8 -to [get_ports out*]

The –through option in the set_max_delay SDC command is not supported.

delay_value

Specifies a floating point number in nanoseconds that represents the required minimum delay value for specified paths.

• If the path starting point is on a sequential device, the tool includes clock skew in the computed delay.
• If the path starting point has an input delay specified, the tool adds that delay value to the path delay.
• If the path ending point is on a sequential device, the tool includes clock skew and library setup time in the computed delay.
• If the ending point has an output delay specified, the tool adds that delay to the path delay.

-from from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-to to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

IGLOO, ProASIC3, SmartFusion, Fusion, ProASIC PLUS, ProASIC (for analysis), Axcelerator, eX (-through option), SX-A (-through option)

This command specifies the required minimum delay for timing paths in the current design. The path length for any startpoint in from_list to any endpoint in to_list must be less than delay_value.

The tool automatically derives the individual minimum delay targets from clock waveforms and port input or output delays. For more information, refer to the create_clock, set_input_delay, and set_output_delay commands.

The minimum delay constraint is a timing exception. This constraint overrides the default single cycle timing relationship for one or more timing paths. This constraint also overrides a multicycle path constraint.

The following example sets a minimum delay by constraining all paths from ff1a:CLK or ff1b:CLK to ff2e:D with a delay less than 5 ns:

set_min_delay 5 -from {ff1a:CLK ff1b:CLK} -to {ff2e:D}

The following example sets a minimum delay by constraining all paths to output ports whose names start by “out” with a delay less than 3.8 ns:

set_min_delay 3.8 -to [get_ports out*]

The –through option in the set_min_delay SDC command is not supported.

ncycles

Specifies an integer value that represents a number of cycles the data path must have for setup or hold check. The value is relative to the starting point or ending point clock, before data is required at the ending point.

-setup

Optional. Applies the cycle value for the setup check only. This option does not affect the hold check. The default hold check will be applied unless you have specified another set_multicycle_path command for the hold value.

-hold

Optional. Applies the cycle value for the hold check only. This option does not affect the setup check.

If you do not specify "-setup" or "-hold", the cycle value is applied to the setup check and the default hold check is performed (ncycles -1).

-from from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-through through_list

Specifies a list of pins or ports through which the multiple cycle paths must pass.

-to to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

IGLOO, ProASIC3, SmartFusion, Fusion, ProASIC PLUS, ProASIC (for analysis), Axcelerator, eX (for analysis), SX-A (for analysis)

Setting multiple cycle paths constraint overrides the single cycle timing relationships between sequential elements by specifying the number of cycles that the data path must have for setup or hold checks. If you change the multiplier, it affects both the setup and hold checks.

False path information always takes precedence over multiple cycle path information. A specific maximum delay constraint overrides a general multiple cycle path constraint.

If you specify more than one object within one -through option, the path passes through any of the objects.

The following example sets all paths between reg1 and reg2 to 3 cycles for setup check. Hold check is measured at the previous edge of the clock at reg2.

set_multicycle_path 3 -from [get_pins {reg1}] –to [get_pins {reg2}]

The following example specifies that four cycles are needed for setup check on all paths starting at the registers in the clock domain ck1. Hold check is further specified with two cycles instead of the three cycles that would have been applied otherwise.

set_multicycle_path 4 -setup -from [get_clocks {ck1}] set_multicycle_path 2 -hold -from [get_clocks {ck1}]

SDC allows multiple priority management on the multiple cycle path constraint depending on the scope of the object accessors. In Microchip design implementation, such priority management is not supported. All multiple cycle path constraints are handled with the same priority.

delay_value

Specifies the amount of time before a clock edge for which the signal is required. This represents a combinational path delay to a register outside the current design plus the library setup time (for maximum output delay) or hold time (for minimum output delay).

-clock clock_ref

Specifies the clock reference to which the specified output delay is related. This is a mandatory argument. If you do not specify -max or -min options, the tool assumes the maximum and minimum input delays to be equal.

-max

Specifies that delay_value refers to the longest path from the specified output. If you do not specify -max or -min options, the tool assumes the maximum and minimum output delays to be equal.

-min

Specifies that delay_value refers to the shortest path from the specified output. If you do not specify -max or -min options, the tool assumes the maximum and minimum output delays to be equal.

-clock_fall

Specifies that the delay is relative to the falling edge of the clock reference. The default is the rising edge.

output_list

Provides a list of output ports in the current design to which delay_value is assigned. If you need to specify more than one object, enclose the objects in braces ({}).

IGLOO, ProASIC3, SmartFusion, Fusion, ProASIC PLUS, ProASIC (for analysis), Axcelerator, eX (for analysis), SX-A (for analysis)

The set_output_delay command sets output path delays on output ports relative to a clock edge. Output ports have no output delay unless you specify it. For in/out (bidirectional) ports, you can specify the path delays for both input and output modes. The tool adds output delay to path delay for paths ending at primary outputs.

The following example sets an output delay of 1.2ns for port OUT1 relative to the rising edge of CLK1:

set_output_delay 1.2 -clock [get_clocks CLK1] [get_ports OUT1]

The following example sets a different maximum and minimum output delay for port OUT1 relative to the falling edge of CLK2:

set_output_delay 1.0 -clock_fall -clock CLK2 –min {OUT1}

set_output_delay 1.4 -clock_fall -clock CLK2 –max {OUT1}

In SDC, the -clock is an optional argument that allows you to set the output delay for combinational designs. Microchip implementation currently requires this option.