6.15 Constraints by File Format: GCF Command Reference

None

ProASIC PLUS and ProASIC

None

If you do not want the Designer software to automatically assign the highest fan-out nets to the available global resources but respect your choice of global nets instead, then include the following statement in a constraint file:

dont_fix_globals;

-eco

Specifies that the constraint file is to be read in eco (engineering change order) mode. In this mode, no errors will be reported when certain nets or instances are not found in the design. Instead a warning is generated.

-initial

Specifies that the constraint file is to be read in initial mode. In this mode, all fixed location statements will be interpreted as initial locations instead.

file (required)

The name of the constraint file, surrounded by double quotes.

ProASIC PLUS and ProASIC

A constraint file can contain multiple read statements. For example, you can put pin assignments in one file, optimization constraints in another, placement constraints in yet another, and read them all in through a master constraint file.

None

The following example instruct the Designer software to use constraints from the GCF files pinmap.gcf and decoder.gcf. A full path specification is given for pinmap.gcf. The file decoder.gcf has no path specification and is assumed to be in the design working directory.

read "/net/aries/designs/pinmap.gcf"; read "decoder.gcf";

number

The maximum number of global resources to use in your design. If you specify a number that exceeds the actual number of global resources available in the device, the Designer software ignores the statement. If you specify 0, no automatic assignment to global resources occurs.

ProASIC PLUS and ProASIC

None

The following example specifies that of the possible four global nets available, the Designer software can automatically promote only two high fan-out nets:

set_auto_global 2;

number

The minimum fan-out for a net. The default number is 32.

ProASIC PLUS and ProASIC

None

For example, the following statement determines that a net must have a fan-out of at least 12 before Designer considers it for automatic promotion to a global resource.

set_auto_global_fanout 12;

hier_net_name

Specifies the name of the hierarchical net(s).

ProASIC PLUS and ProASIC

None

set_global u1/u3/net_clk, u3/u1/net_7;

hier_net_name

Specifies the name of the hierarchical net(s).

ProASIC PLUS and ProASIC

None

set_noglobal u2/u8/net_14;

spine

Specifies one of the spines: T1 to T<n> or B1 to B<n>.

net_name

Specifies the name of a net.

ProASIC PLUS and ProASIC

None

If you specify the spine rectangle as B1, T3, the driven instances of the given net get a region constraint which encloses the rectangle, including the spine rectangle B1, T1, B2, T2, B2, T3.

use_global B1, T3 <net_name>;

The constraint tries to place the driver as close to the center of the rectangle as possible.

The RAMs and I/Os are assigned to the LocalClock region unless the Compile option “Include RAM and I/O in Spine and Net Regions” is cleared. For designs created with v5.1 or earlier, this option is cleared by default. See "Compile Options" in the online help for more information.

You can specify the following type of rectangles:

• Bn, Bm : n<=m will mean Bn, Bn+1, ... Bm
• Tn, Tm : n<=m will mean Tn, Tn+1, ... Tm
• Bn, Tm : n<=m will mean Bn, Tn, Bn+1,Tn+1 ... Bm, Tm
• Tn, Bm : n<=m will mean Bn, Tn, Bn+1,Tn+1 ... Bm, Tm The following table summarizes the available spines.

  Table 6-8. Global Spine Usage

  Device	Spine
  A500K050	T1 to T3
  	B1 to B3
  A500K130	T1 to T5
  	B1 to B5
  A500K180	T1 to T6
  	B1 to B6
  A500K270	T1 to T7
  	B1 to B7
  APA075	T1 to T3
  	B1 to B3
  APA150	T1 to T4
  	B1 to B4
  APA300	T1 to T4
  	B1 to B4
  APA450	T1 to T6
  	B1 to B4
  APA600	T1 to T7
  	B1 to B7
  APA750	T1 to T8
  	B1 to B8
  APA1000	T1 to T11
  	B1 to B11

  T1 and B1 are the leftmost top and bottom global spines, respectively.

[option ]

Specifies the netlist optimization option to turn off and preserve.

Option	Description
buffer	Prevents buffers from being removed from the design
inverter	Prevents inverters from being removed from the design
const	Replaces all logical elements with one or more inputs connected to a constant (logical "1" or "0") by the appropriate logic function. If the replacement logic function is identified as an inverter or buffer, that element is removed.
dangling	Removes all cells driving unconnected nets

ProASIC PLUS and ProASIC

This statement does not optimize your buffers or inverters; instead, it prevents them from being removed. When followed by one or more of the netlist optimization options, this statement turns off the named option (and preserves it).

If you have buffers or inverters that are connected to global nets, promoted global nets, or spine nets, this command is ignored and buffers and inverters are removed. To avoid removing them, use the dont_touch option.

None

dont_optimize buffer inverter;

hier_instance_name [hier_instance_name ... ]

Specifies the name of the hierarchical instance(s) for which you want to disable optimization.

ProASIC PLUS and ProASIC

You can use the wildcard character (*) to isolate all sub-blocks under the named block. If you use this constraint, any instances (including buffers and inverters that are connected to global nets, promoted global nets, and spine nets) stay intact.

Use “dont_touch” with instance names only. You cannot use this constraint with net names.

The statement in this example will enable only the buffer and inverter optimization types and optimization will be done on all instances except those contained in the block called /U1/myblock.

dont_touch /U1/myblock/*;

[{ option }]

Specifies the netlist optimization option to turn on.

Option	Description
	Removes all buffers in the design, provided you have not exceeded the maximum fan-out
inverter	Removes all inverters in the design, provided you have not exceeded the maximum fan-out
const	Replaces all logical elements with one or more inputs connected to a constant (logical “1” or “0”) by the appropriate logic function. If the replacement logic function is identified as an inverter or buffer, that element is removed.
dangling	Recursively removes all cells driving unconnected nets

ProASIC PLUS and ProASIC

None

optimize buffer inverter;

ProASIC PLUS and ProASIC

The set_max_fanout constraint is optimized to accept individual net names. If you specify a net name, the set_max_fanout constraint applies only to the named net or nets and not to the entire design.

The buffers and inverters are not removed if the fan-out for the given net exceeds the given limit. If no net name is given, then the command is applied to all the nets in the design. The net name can be a simple net or a name having wildcard characters.

None

set_max_fanout 15 testNet*;

Use the IO_ARRIVAL_TIMES section to define the arrival time to an input port.

[early_arrival_time:] late_arrival_time timeunit {source_io_list} EXCEPT {source_io_list}.

{early, late}_arrival_time

Signal arrival time relative to the reference time.

source_io_list

An INPAD or primary input pin.

The section IO_ARRIVAL_TIMES can be empty. For example,

SECTION IO_ARRIVAL_TIMES. END.

is entirely equivalent to

SECTION IO_ARRIVAL_TIMES.

0 0 {INPAD}. END

Use the MAX_DELAYS and MIN_DELAYS section to specify the maximum and minimum delays.

DELAY value timeunit; SOURCE {source_name_list}; SINK {sink_name_list}; [STOP

{stop_name_list}]; [PASS {bypass_name_list}].

DELAY value

Specifies an integer.

timeunit

Allows {PS, NS, US}.

source_name_list

A list of signal sources. It can be one of the following: a macro output pin, macro name, or primary input.

sink_name_list

A list of signal destinations. It can be a name of a macro or a primary output.

stop_name_list

The list of pin names through which further propagation of signals will not be considered. This allows you to eliminate certain paths from consideration.

bypass_name_list

The list of latches which are allowed to be intermediate path points. By default, latches are considered to be sinks or path terminals.

INPAD/OUTPAD/GATED

Valid values for any of the lists, such as source_name_list or stop_name_list.

Normally there is no need to specify any timing requirements from any source to any sink clocked by an external global clock. This timing requirement can be generated automatically from the GLOBAL_CLOCK specifications and the sequential elements setup and hold times. For example, the timing constraint from a primary input to a sequential element can be derived from the sequential elements clocking waveform and the signal arrival time of the primary input.

A problem exists when two different internally-generated clock signals interact. This is due to the unpredictable and unknown skew between the two clock networks because of the routing delays from:

PAD >> internalMacro >> CLKINT

where CLKINT is the input pin of the global clock distribution network. The automatically generated path constraints will not incorporate the skew between the two clocks. In such cases, the path constraints should be expressed explicitly using the MAX/MIN_DELAYS section.

The most stringent timing constraint dominates. Hence, all general constraints should be looser than the specific constraints. For example, in the following example, the 26.0ns constraint dominates the 42.0ns constraint:

DELAY 42.0 ns SOURCE INPAD SINK OUTPAD.

DELAY 26.0 ns SOURCE {$1I23:Q $1I24:Q} SINK {ack_0}.

If the general constraint is tighter than the specific constraint, the specific constraint will effectively become a no-operation. In the following example, the looser constraint of 42.0ns has no effect since the general constraint of 26.0ns dominates.

DELAY 26.0 ns SOURCE INPAD SINK OUTPAD.

DELAY 42.0 ns SOURCE {$1I23:Q $1I24:Q} SINK {ack_0}.

The section MAX_DELAYS can be empty if there are no purely combinatorial paths from external sources to external sinks, and if every sequential element in the design is clocked by an external global clock. In this case, the timing constraints are generated automatically using the information in the GLOBAL_CLOCK section. Likewise, the MIN_DELAYS section can be empty.

One final word about external/internal sinks and sources with regard to the flip-flops and/or latches in the IOs: these flip-flops act as internal, not external, sources/sinks.

WAVEFORM clkname RISE value FALL value PERIOD value [EXCEPT SOURCE {sequential list }| EXCEPT SINK{sequential list}].

Use the GLOBAL_CLOCKS section to describe the clock waveforms from the global clock distribution networks. Local clocks, such as gated clocks, are not directly supported. The clock waveforms are used to generate the timing constraints of the paths between two sequential elements. To allow more user control when clocks interact, there are provisions to specify the clock period transitions, which should be considered. By default, the closest transitions are used when two clocks interact. The clock waveform specification has the following format:

clkname

Specifies the name of the macro driving the clock network.

RISE/FALL/PERIODvalue

Specify the value as either an integer or a floating point number followed by an unit selected from {NS, US, PS}. The default time unit is 0.1ns.

EXCEPT {SOURCE|SINK} {sequential list}

Specify the list of sequential elements which should not be included as endpoints in the automatically generated paths involving sequential elements.

clkA/clkB

The name of the macro driving the clock network.

EXCEPT {seqlist}.

By default all sequential elements clocked by the clock driver are included. The EXCEPT seqlist is a list of all the sequential elements or specific pins to be excluded.

CYCLE value

By default, the closest transitions are considered. CYCLE provides the ability to use transitions from one or more clock periods past the closest transition. CYCLE zero indicates the closest transitions. CYCLE one skips the closest set of transitions and uses the next set of transitions. The term cycle is used to avoid confusion with the term period in the clock waveform specification. This allows you to specify a cycling-stealing clocking regime.

{<pinNameList>}. End.

Use the GLOBAL_STOPS section to disable dont care/false paths by preventing the specified pins from being used in ANY timingcritical paths. Any path involving pins that appear in this section should be removed from consideration.

Use the PIN_LOADS section to define the capacitance loading and logic (TTL/CMOS) at a package pin. The default logic family is TTL.

capValue capUnit [TTL/CMOS]{[macList|pinList]} [EXCEPT {}].