6.3 Basic Concepts

The names of ports, instances, and nets in an imported netlist are sometimes referred to as their original names. Port names appear exactly as they are defined in a netlist. For example, a port named A/B appears as A/B in ChipPlanner, PinEditor, and I/O Attribute Editor in MultiView Navigator. Instances and nets display the original names plus an escape character (\) before each backslash (/) and each slash (\) that is not a hierarchy separator. For example, the instance named A/\B is displayed as A\/\\B.

Following are Designer's naming conventions by device.

Specifying clock constraints is the most effective way of constraining and verifying the timing behavior of a sequential design. You must use clock constraints to meet your performance goals and to quickly reach timing closure.

A region is a user-defined area on a chip into which you can constrain the physical placement of one or more macros. You can also constrain macros containing multiple tiles for cores, RAMs, and I/Os. The floorplanning process usually requires you to create several regions and assign logic to them. Logic can include core logic, memory, and I/O modules. When you run the place-and-route tool, it places the logic into their assigned regions.

Some regions are user-defined and others are automatically created by the tools to meet routing requirements (for example, Local clock regions).

You can use region constraints to:

• Create user-defined regions such as Inclusive, Exclusive, Empty, LocalClock, and QuadrantClock
• Assign and unassign macros to user-defined regions
• Constrain all the macros connected to a net by assigning them to a specific net region
• Move regions from one set of co-ordinates to another

Each core, RAM, and I/O macro in the design is associated with a location on the device. When you run the place-and-route tool, it places all of your logic into their assigned locations.

You can use location constraints to:

• Overwrite the existing placements of macros
• Tell the place-and-route tool where to initially place the macros
• Assign I/O macros to specific pins to meet your board's requirements

I/O attributes are the characteristics of logic macros or nets in your design. They indicate placement, implementation, naming, directionality, and other characteristics. This information is used by the design implementation software during the place-and-route of a design.

Input and output attributes are described in the documentation for the I/O Attribute Editor. Attributes applicable to a specific tool are described in the documentation for that tool.

See the topics in I/O Attributes for more detailed information about each attribute.

The I/O Attribute Editor from MultiView Navigator is now integrated in the Libero IDE Project Manager and in SmartDesign. SmartDesign automatically passes I/O constraints to Designer.

You can define physical I/O constraints using I/O Attribute Editor from within the Project Manager.

You can start I/O Attribute Editor either from SmartDesign or by opening a PDC file from the Design Explorer.

To start the I/O Attribute Editor from SmartDesign, from the SmartDesign menu, choose Show I/O Attribute Editor View. The I/O Attribute Editor opens in front of the SmartDesign Canvas as shown below.

To open a PDC file from Design Explorer, right-click the file you want to open in the Files tab, and choose Open with I/O Attribute Editor as shown below.

You can either load an existing PDC into the I/O Attribute Editor, or you can create a new PDC file using the I/O Attribute Editor. When you load an existing PDC file, only the I/O-related constraints are shown in the I/O Attribute Editor. The other constraints are preserved and inserted at the end of the new, saved file.

I/O Attribute Editor enables you to view, create, and modify your physical design constraint (PDC) files. The Files tab lists your constraint files in alphabetical order.

You can save your constraint file at any time.

I/O Attribute Editor (v6.2 and higher) includes a Package Pins view in addition to its Ports view. Click the Package Pins tab to display your I/O attributes by package pin number. This view makes it much easier to assign address/data ports to adjacent pins. Additionally, it enables you to assign VREF pins (which you cannot do in Ports view) and to sort on banks.

You edit I/O attributes using the I/O Attribute Editor. It displays all assigned and unassigned I/O macros and their attributes in tabular format.

Use the I/O Attribute Editor to view, sort, select, and edit common and device-specific I/O attributes.

You can view the I/O attributes by port or by package pin. Click the Ports tab to view I/O attributes by port name. Click the Package Pins tab to view I/O attributes by pin number.

Each row corresponds to an I/O macro (port) or a pin in the design, depending on the view displayed. The column headings specify the names of the I/O attributes in your design. The first four column headings are standard for all families so they will not change. However, the other column headings will change depending on the family you are designing for. For some I/O attributes, you will choose from a drop-down menu; for others, you might enter a value.

To edit I/O attributes:

1. Select an I/O standard for each I/O macro in your device.
2. Select I/O attributes that are available for your selected I/O standard.

For descriptions of individual I/O attributes and support by family, refer to the I/O Attributes Reference section of the Design Constraints Guide.

To edit multiple rows:

1. Select the rows to edit. To select consecutive rows, click the first row, press and hold down the SHIFT key, and then click the last row. To select rows that are not consecutive, press and hold down the CTRL key, and then click each row to select. Continue to hold down the SHIFT or CTRL key.
2. While still holding down the SHIFT or CTRL key, click in the cell containing the value you want to change. Release the SHIFT or CTRL key, and then release the mouse button.

The change occurs in all selected rows.

You can also select an entire column, which enables you to edit all rows in that column.

You can sort rows by column in either ascending or descending order.

To sort I/O macros by attributes:

• Double-click a column heading to sort the table rows in ascending order.
• Double-click the column again to sort the table rows in descending order.

When sorted, an arrowhead appears in the column header to indicate the sort order.

When viewing and editing your input/output attributes, you can format the table to display only the attributes you want to see. Clicking the top-left cell selects all rows in the I/O Attribute Editor.

To hide one or more rows or columns:

1. Select the row(s) or column(s) you want to hide from view.
2. From the I/O Attribute Editor> Format menu, choose Row > Hide or Column > Hide, or right-click the row or column header and choose Hide from the right-click menu.

To show a hidden row or column:

1. Select a range of rows or columns that span one or more hidden rows or columns.
2. From the I/O Attribute Editor>Format menu, choose Row > Unhide or Column > Unhide, or right-click the row or column header and choose Unhide from the right-click menu.

Unhide also works for a selected column that has a hidden column to its immediate left or right (or both).

You can “freeze” (or lock) one or more columns so they remain visible on the screen as you scroll horizontally.

To freeze or lock one or more columns:

1. Select the column to the right of the last column to freeze.
2. From the I/O Attribute Editor>Format menu, choose Column > Freeze Pane, or right-click the column and choose Freeze Pane from the right-click menu.

To unfreeze one or more frozen columns, from the I/O Attribute Editor>Format menu, choose Column > Unfreeze Pane, or right-click any column header and choose Unfreeze Pane from the right-click menu. All frozen columns are unfrozen.

You can also resize all the columns and rows at once so their entire contents are visible.

You must unfreeze the current locked group before you can freeze another group.

To display a column's entire contents within it:

1. Select the column(s) you want to display.
2. From the I/O Attribute Editor>Format menu, choose Column >AutoFit. The width of the column either expands or contracts to fit only the cell heading and cell contents.

The procedure for manually assigning technologies to I/O banks differs depending on whether you are designing for IGLOO, Fusion, ProASIC3, or Axcelerator devices.

To assign technologies to I/O banks in IGLOOe, Fusion, ProASIC3L, ProASIC3E, and Axcelerator devices:

1. Select an I/O bank in either ChipPlanner or PinEditor.
2. From the Edit menu, choose I/O Bank Settings.
3. In the I/O Bank Settings dialog box, select the technologies, and click Apply.

   Selecting a standard selects all compatible standards and grays out incompatible ones. For example, selecting LVTTL also selects PCI, PCIX, and LVPECL, since they all have the same VCCI. Further, selecting GTLP (3.3 V) disables SSTL3 as an option because the VREFs of the two are not the same. Once you click Apply, the I/O bank is assigned the selected standards. Any I/O of the selected types can now be assigned to that I/O bank. Any previously assigned I/Os in the bank that are no longer compatible with the standards applied are unassigned.

4. Click More Attributes to set the low-power mode and input delay. (These attributes are supported in Axcelerator devices only.)
5. Assign I/O standards to other banks by selecting the banks from the list and assigning standards. Any banks not assigned I/O standards use the default standard selected in the Device Selection Wizard.
6. Leave the Use default pins for VREFs option selected to set default VREF pins and unset non-default VREF pins. If you unselect this option when setting a new VREF technology, no VREF pins are set. If you unselect this option when default VREF pins are already set, it unsets them.

   If the Use default pins for VREFs option is selected when you click OK or Apply, the software: 1) determines if setting default VREF pins causes any I/O macros to become unassigned, and if so, displays a warning message enabling you to cancel this operation, 2) determines if unsetting non-default VREF pins causes any I/O macros to become unassigned, and if so, displays a warning message enabling you to cancel this operation, and 3) sets default VREF pins and unsets non-default VREF pins.

7. Click OK. Using PinEditor, proceed to assign I/Os with the same standards to the appropriate banks.

   

If VREF pins can be assigned, you must assign at least one VREF pin before running Layout. See "Assigning VREF Pins" in this guide for more information.

If you use I/O standards that need reference voltage, make sure to assign VREF pins. Microchip strongly recommends you use the defaults. VREF pins appear in red in ChipPlanner and are labeled VREF in PinEditor.

To set the low-power mode and input delay (for Axcelerator devices only):

1. Click More Attributes in the I/O Bank Settings dialog box.
2. Drag the slider bar to the desired delay. The delay is bank specific.
3. Click View All Delays to see all the delay values (Best, Worst, Typical, Rise-Rise, Fall-Fall) for the input delay selected. You must select a technology to see the input delays.
4. Click OK.

To assign technologies to I/O banks in ProASIC3 and IGLOO devices:

1. Select an I/O bank in either ChipPlanner or PinEditor.
2. From the Edit menu, choose I/O Bank Settings.
3. In the I/O Bank Settings dialog box, select the technologies, and click Apply.

   Selecting a standard selects all compatible standards and grays out incompatible ones. For example, selecting LVTTL also selects PCI, PCIX, and LVPECL, since they all have the same VCCI. Note that LVDS is available only for banks 1 and 3. Once you click Apply, the I/O bank is assigned the selected standards. Any I/O of the selected types can now be assigned to that I/O bank. Any previously assigned I/Os in the bank that are no longer compatible with the standards applied are unassigned.

4. Assign I/O standards to other banks by selecting the banks from the list and assigning standards. Any banks not assigned I/O standards use the default standard selected in the Device Selection Wizard.
5. Click OK. Using PinEditor, proceed to assign I/Os with the same standards to the appropriate banks.

   

You cannot assign VREF pins in ProASIC3 and IGLOO devices. You can assign VREF pins only to IGLOOe, Fusion, ProASIC3L (A3PE3000L die only), and ProASIC3E devices.

The I/O Bank Assigner (IOBA) tool runs automatically when you run Layout. You can also use this tool from within the MultiView Navigator or from within Libero Project Manager. The I/O Bank Assigner tool automatically assign technologies and VREF pins (if required) to every I/O bank that does not currently have any technologies assigned to it. This tool is available when at least one I/O bank is unassigned.

Each time you run the I/O Bank Assigner, it unassigns all technologies from all I/O banks and then re-assigns them when it finds a feasible solution. To prevent I/O Bank Assigner from unassigning and re-assigning I/O technologies each time you run it, lock the I/O banks by selecting Locked in the I/O Bank Settings Dialog Box or by importing the

,set_iobanks PDC command with its -fixed argument set to "yes".

To automatically assign technologies to I/O banks:

• In Project Manager, from the I/O Attribute Editor menu, choose Tools>Auto-Assign I/O Banks.
• In MultiView Navigator, from the Tools menu, choose Auto-Assign I/O Banks. You can also click the I/O Bank Assigner's toolbar button shown below.

Messages appear in the Output window informing you when the automatic I/O bank assignment begins and ends. If the assignment is successful, "I/O Bank Assigner completed successfully" appears in the Output window.

If the assignment is not successful, an error message appears in the Output window. Click an underlined "Error" or "Info" message to display more information.

All I/O technologies assigned to I/O banks by the I/O Bank Assigner in Layout are unlocked.

To undo the I/O bank assignments, choose Undo from the Edit menu. Undo removes the I/O technologies assigned by the I/O Bank Assigner. It does not remove the I/O technologies previously assigned.

To redo the changes undone by the Undo command, choose Redo from the Edit menu.

If you need to clear I/O bank assignments made before using the Undo command, you can manually unassign or re-assign I/O technologies to banks. To do so, choose I/O Bank Settings from the Edit menu to display the I/O Bank Settings dialog box.

With this feature, you can begin a design with a larger device that you intend to implement later with a smaller device. Because there might be some pins on the smaller device that are not bonded, you want to make sure that the pin assignments created on the larger device are compatible with the pins on the smaller device. This feature reserves the pins on the larger device that are not bonded on the smaller device.

Pins in the current device that are not bonded in the target device will be marked as "reserved."

You can explicitly reserve a pin in PinEditor or I/O Attribute Editor (Package Pins view). You can also reserve a pin by importing a PDC constraint file with the reserve PDC command.

To explicitly reserve a pin in PinEditor:

• Select the pin to reserve, right-click it, and choose Reserve Pin from the right-click menu. (See screen below.) Repeat for each pin to reserve.

To unreserve a reserved pin from the right-click menu in PinEditor, select the pin to unreserve, right-click it, and choose Reserve Pin to remove the checkmark.

To explicitly reserve a pin in I/O Attribute Editor:

• In Package Pins view, select the User Reserved check box associated with the pin to reserve. (See screen below.) Repeat for each pin to reserve.

To automatically reserve pins that are not bonded in a destination device for migration, follow these steps:

1. In PinEditor, from the Edit menu, choose Reserve Pins for Migration. The Reserve Pins for Migration dialog box appears. The current device for which the pins will be reserved appears in the Reserve pins in the current device text box.
2. From the "that are not bonded in the target device" drop-down list, select the target device to which you will be migrating your design.
3. Unselect the Keep explicitly-reserved pins check box if you do not want to save the pins that are currently explicitly reserved.

Choose Undo Reserve Package Pin from the Edit menu to unreserve the last pin you reserved.

To reserve pins with a PDC file:

1. Open the PDC file to edit.
2. Use the reserve command to specify the names of the pins to reserve.

To unreserve pins with a PDC file:

1. Open the PDC file to edit.
2. Use the unreserve command to specify the names of the pins to unreserve.

   SX-A devices do not support the reserved pins feature.

Use the I/O Standard column to select an I/O specification for each pin.

If required to match the I/O standard, other I/O attributes, such as I/O threshold, slew, and loading, are automatically set to their default settings; you cannot edit these defaults.

You can change the I/O standards only for a generic I/O buffer to any of the legal I/O standards.

To specify an I/O standard:

1. Click the I/O Standard cell in the desired macro row.
2. Type or select a supported I/O standard from the drop-down list.

For devices that support I/O banks (for example, Axcelerator devices), the list is restricted to legal choices only. When an I/O is assigned, the I/O standards available for that I/O are limited to what the I/O bank location can support.

Changing an I/O standard may also unassign existing I/Os. In addition, when a macro is assigned an I/O standard, the I/O bank is automatically assigned the voltages VCCI and VREF, if necessary. Unassigning this macro will undo these assignments as well.