6.4 I/O Attributes

Displays the name of the bank to which the I/O macro has been assigned. You cannot change the bank name.

Indicates whether the port currently belongs to a group.

Use this attribute to assign a port to a group or unassign a port from a group.

Preserves the previous state of the I/O. By default, all the I/Os become tristated when the device goes into Flash*Freeze mode. (A tristatable I/O is an I/O with three output states: high, low, and high impedance.) You can override this default using the hold_state attribute. When you set the hold_state to True, the I/O remains in the same state in which it was functioning before the device went into Flash*Freeze mode.

Indicates whether the I/O pin is hot swappable.

If you see either a checkmark or ON (all standards except PCI and PCIX), it means that a clamp diode is NOT included to allow proper hot-swap behavior. If you do not see a checkmark or you see "OFF" (PCI and PCIX only), it means that a clamp diode is included as required by those specifications, but the I/O is NOT hot swappable.

Indicates whether the input path delay elements are to be programmed. If they will be programmed, this option adds the specified input delay to the input path.

Use this attribute to turn the input delay on or off.

For ProASIC3E devices, you specify the input delay per pin. You will see the actual delay only in Timer or in the SDF file.

The actual input delay is a function of the operating conditions and is automatically computed by the delay extractor when a timing report is generated.

For Axcelerator devices, you specify the input delay per bank. You then set its input delay with the slider in the More I/O Bank Attributes Dialog Box. Possible values are 0 to 31.

Use the I/O standard attribute to assign an I/O standard to an I/O macro.

* Supports LVPECL but only on dedicated LVPECL I/Os.

Voltage referenced I/O inputs require an input referenced voltage (VREF). You must assign VREF pins to IGLOOe, ProASIC3E, and Axcelerator devices before running Layout.

IGLOO, ProASIC3, SmartFusion, Fusion and Axcelerator families support multiple I/O standards (with different I/O voltages) in a single die. You can use I/O Attribute Editor to set I/O standards and attributes, or alternatively you can export and import this information using a PDC file.

Not all devices support all I/O standards. The following table shows you which I/O standards are supported by each device.

*Supported only on dedicated LVPECL I/Os.

For a list of I/O standards for all other families, refer to the datasheet for your specific device.

Indicates the compatible threshold level for inputs and outputs.

* For SX, there is an Output Level option, which is the same as the threshold option. See Output level for more information.

Use this attribute to set the compatible threshold level for inputs and outputs. The values you can choose from depend on which device you selected. The default I/O threshold displayed is based upon the I/O standard. If you want to set the I/O threshold independently of the I/O specification, you must select CUSTOM in the I/O standard cell.

Indicates whether you can change the current pin assignment during layout.

Use this attribute to lock or unlock the pin assignment. Selecting the check box locks the pin assignment. Clearing the check box unlocks the pin assignment. If locked, you cannot change the pin assignment. If not locked, you can.

The term "fixed" for SX-A, SX, RTSX-S, eX,and MX devices means "locked."

Indicates the type of I/O macro. This value is read only and is applicable only to the I/O Attribute Editor tool (that is, you cannot use it in GCF or PDC files).

Every I/O standard has an output drive preset; however, for some I/O standards, you can choose which one to use. The higher the drive, the faster the I/O. The faster the I/O, the more power consumed by the I/O.

Use this attribute to set the strength of the output buffer to between 2 and 24 mA, weakest to strongest, depending on your device family. The LVTTL output buffer has four programmable settings of its drive strength. Other I/O standards have full strength.

The list of I/O standards for which you can change the output drive and the list of values you can assign for each I/O standard is family-specific. Refer to the datasheet for your device for more information.

Indicates the output-capacitance value based on the I/O standard selected in the I/O Standard cell. This option is not available in software.

You can enter a capacitative load as an integral number of picofarads. The default value varies by device family. If necessary, you can change the output capacitance default setting to improve timing definition and analysis. Both the capacitive loading on the board and the Vil/Vih trip points of driven devices affect output-propagation delay.

Timer, Timing-Driven Layout, Timing Report, and Back-Annotation automatically uses the modified delay model for delay calculations.

Use the Output Level attribute to assign an I/O output level to an I/O pin.

The I/O pin functions as an input, output, tristate, or bidirectional buffer. Based on certain configurations, input and output levels are compatible with standard TTL, LVTTL, 3.3 V PCI or 5.0V PCI specifications. Unused I/O pins are automatically tristated by the Designer software.

LVTTLCMOS, or PCI.

LVTTL

Use this attribute to change a pin assignment by choosing one of the legal values from the drop-down list. If the pin has been assigned, the pin number appears in this column. If it hasn't been assigned, "Unassigned" appears in this column.

Indicates the port name of the I/O macro. This value is read only.

Indicates the power-up state of the pin. All I/Os are equipped with pull-up and pull-down resistors, which are enabled during power-up. These resistors are disabled just before VCCA reaches 2.5 V, and then the I/Os behave according to the design. For eX and SX-A, this configurable I/O state does not eliminate the risk of an I/O driving a temporary unknown state near the end of the power-up sequence when VCCI is powered up before VCCA. For RTSX-S, the outputs will drive according to the design, when the resistors become disabled regardless of the power-up sequence.

Use this attribute to set the power-up state. Your choices are None, High, and Low. The default value is None. The only exception to this is an I/O that exists in the netlist as a port, is not connected to the core, and is configured as an Output Buffer. In that case, the default setting will be Low.

Allows inclusion of a weak resistor for either pull-up or pull-down of the input buffer.

Use this attribute to set the resistor pull. Your choices are None, Up (pull-up), or Down (pull-down). The default value is None except when an I/O exists in the netlist as a port, is not connected to the core, and is configured as an output buffer. In that case, the default setting is for a weak pull-down.

A schmitt trigger is a buffer used to convert a slow or noisy input signal into a clean one before passing it to the FPGA. This is a simple, low-cost solution for a user working with low slew-rate signals. Using schmitt-trigger buffers guarantees a fast, noise-free, input signal to the FPGA.

Microchip recommends that you use a schmitt trigger to buffer a signal if input slew rates fall below the values outlined in the specification for SX-A and RTSX-S devices. Depending on the application, different schmitt-trigger buffers can be used to fulfill the requirements.

Schmitt-trigger buffers are categorized in three configurations:

• Fixed threshold voltages with non-inverted outputs
• Fixed threshold voltages and inverted outputs
• Variable threshold voltages with non-inverted outputs

With the aid of schmitt-trigger buffers, low slew-rate applications can also be handled with ease. Implementation of these buffers is simple, not expensive, and flexible in that different configurations are possible depending on the application. The characteristics of schmitt-trigger buffers (e.g. threshold voltage) can be fixed or user-adjustable if required.

*Although ProASIC PLUS supports the schmitt-trigger attribute,you cannot edit this attribute with the MultiView Navigator tools. Instead, it has to be instantiated in the schematic or the netlist.

A schmitt trigger has two possible states: on or off. The trigger for this circuit to change states is the input voltage level. That is, the output state depends on the input level, and will change only as the input crosses a pre-defined threshold.

For more information, please see the "Using Schmitt Triggers for Low Slew-Rate Input" Application Note on the Microchip website.

Indicates whether there is a fixed additional delay between the enable/disable time for a tristatable I/O. (A tristatable I/O is an I/O with three output states: high, low, and high impedance.) 2 ns delay on rising edge, 0 ns delay on falling edge.

You can set the skew for a clock to either on or off.

A Tri State or "tristatable" logic gate has three output states: high, low, and high impedance. In a high impedance state, the output acts like a resistor with infinite resistance, which means the output is disconnected from the rest of the circuit.

Indicates the slew rate for output buffers. Generally, available slew rates are high and low.

You can set the slew rate for the output buffer to either high or low. The output buffer has a programmable slew rate for both high-to-low and low-to-high transitions. The low slew rate is incompatible with 3.3 V PCI requirements.

For ProASIC3 families, you can edit the slew for designs using LVTTL, all LVCMOS, or PCIX I/O standards. The other I/O standards have a preset slew value. For the Axcelerator family, you can edit the slew only for designs using the LVTTL I/O standard. For those devices that support additional slew values, Microchip recommends that you use the high and low values and let the software map to the appropriate absolute slew value. The default slew displayed in the I/O Attribute Editor is based on the selected I/O standard. For example, PCI mode sets the default output slew rate to High.

One way to eliminate problems with low slew rate is with external schmitt triggers.

In some applications, you may require a very fast (i.e. high slew rate) signal, which approaches an ideal switching transition. You can accomplish this by either reducing the track resistance and/or capacitance on the board or increasing the drive capability of the input signal. Both of these options are generally time consuming and costly. Furthermore, the closer the input signal approaches an ideal one, the greater the likelihood of unwanted effects such as increased peak current, capacitive coupling, and ground bounce. In many cases, you may want to incorporate a finite amount of slew rate into your signal to reduce these effects. On the other hand, if an input signal becomes too slow (i.e. low slew rate), then noise around the FPGA's input voltage threshold can cause multiple state changes. During the transition time, both input buffer transistors could potentially turn on at the same time, which could result in the output of the buffer to oscillate unpredictably. In this situation, the input buffer could still pass signals. However, these short, unpredictable oscillations would likely cause the device to malfunction. Microchip has performed reliability tests on RTSX-S devices and the reliability of the device is guaranteed for signals with slew rates up to 500µs. This test has not been performed on the SX-A family. For more information, see the RTSX-S TR/TF Experiment report on the Microchip website.

The input and output registers for each individual I/O can be activated by selecting the check box associated with an I/O. The I/O registers are NOT selected by default.

You can explicitly reserve a pin in one of the following ways:

• In the I/O Attribute Editor (Package Pins view), select the User Reserved check box associated with the pin to reserve.
• Select a pin in PinEditor, right-click it, and choose Reserve Pin from the right-click menu.
• User the reserve command in a PDC constraint file.