6.10 Constraints by Name: Physical

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to set the location of a pin.

For IGLOO, ProASIC3 and Axcelerator, you can use the set_io command in a PDC file to assign I/Os to pins as well as set the attributes of an I/O. For ProASIC PLUS and ProASIC, you can use the set_io command in a GCF file to assign package pins to I/O ports or to locate I/O ports at a specified side or location of a device. For earlier families, you can use a PIN file to set the location of a pin.

You can use one or more of the following commands or GUI tools to assign an I/O to a pin:

• PDC - set_io
• GCF - set_io
• PIN - PIN <pin_name>; PIN:<package_pin_number>
• PinEditor (MVN) - Assigning pins
• PinEditor (non-MVN) - Assigning pins

You can also set the location of a pin using the pin_assign command in a Tcl script.

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to assign one or more I/O macros to a specific location. You can define the location using array co-ordinates.

By confining macros to one area, you can keep the nets connected to that area, resulting in better timing and better floorplanning. Sometimes placing some macros at specific locations can also result in meeting timing closures.

You can use one or more of the following commands or GUI tools to assign a macro to a location:

• PDC - set_location
• GCF - set_location
• ChipEditor - Assigning Logic

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to assign one or more macros to a specific region.

By confining macros to one area, you can keep the nets connected to that area, resulting in better timing and better floorplanning.

For IGLOO, ProASIC3, Fusion, SmartFusion and Axcelerator devices, you can use the define_region PDC command to create a region, and then use the assign_region PDC command to constrain a set of existing macros to that region.

For ProASIC PLUS and ProASIC, you can use the set_location GCF command to both create a region and constrain an existing set of macros to it at the same time. To define a region with the set_location command in a GCF file, you must specify the array coordinates for a rectangular area, for example, x1, y1, x2, y2.

You can also use the MultiView Navigator tool to create regions for any of the supported families.

You can use one or more of the following commands or GUI tools to assign a macro to a region:

• PDC - assign_region
• GCF - set_location
• ChipPlanner - Assigning a macro to a region

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to assign high fan-out nets to global clock networks by promoting the net using an internal global macro.

If there are enough global clock routing resources available in a device, you can promote regular nets that have high fan-out to the dedicated fast global clock routing resources which can lead to better performance for your design. This is achieved by automatically inserting an internal global macro on a net which guides the place-and-route tool to

promote that particular net to a global clock resource. This internal global macro is CLKINT for IGLOO, ProASIC3, SmartFusion and Fusion families, GLINT for ProASIC PLUS and ProASIC families, and either HCLKINT or CLKINT for Axcelerator families.

You can use one or more of the following commands or GUI tools to assign a net to a global clock:

• PDC - assign_global_clock
• GCF - set_global

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to assign regular nets to local clock routing or to LocalClock regions. This results in the creation of a LocalClock region that spans the area of the local clock net.

If there are enough local clock resources but not enough global clock routing resources available in a device, you can assign regular nets that have high fan-out to the dedicated local clock routing resources which can lead to better performance for your design.

You can use one or more of the following commands or GUI tools to assign a net to a local clock:

• PDC -assign_local_clock
• GCF - use_global
• ChipPlanner - Creating LocalClock Regions

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to assign regular nets to quadrant clock routing. This results in the creation of a QuadrantClock region that spans the area of the quadrant clock net.

If there are enough quadrant clock resources but not enough global clock routing resources available in a device, you can promote regular nets that have high fan-out to the dedicated quadrant clock routing resources which can lead to better performance for your design.

You can use one or more of the following commands or GUI tools to assign a net to a local clock:

• PDC - assign_quadrant_clock
• ChipPlanner - Creating QuadrantClock Regions

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to place all the loads of a net into a given region. This constraint is useful for high fan-out or critical path nets or bus control logic.

Constraining nets to a region helps to control the connection delays from the net's driver to the logic instances it fans out to. You can adjust the size of the region to pack logic more closely together, hence, improving its net delays.

Suppose you have a global net with loads that span across the whole chip. When you constrain this net to a specific region, you force the loads of this global net into the given region. Forcing loads into a region frees up some areas that were previously used. You can then use these free areas for high-speed local clocks/spines.

Macros connected to a specific net can be assigned to a region in the device. The region can be defined using the define_region PDC command. With the set_net_region GCF command, you can use array coordinates to define the region into which you want to place all the connected instances, driver, and all the driven instances for the net(s).

When assigning a net to a region, all of the logic driven by that net will be assigned to that region.

Using Regions for Critical Path and High Fan-out Nets

You should assign high fan-out or critical path nets to a region only after you have used up your global routing and clock spine networks. If you have determined, through timing analysis, that certain long delay nets are creating timing violations, assign them to regions to reduce their delays.

Before creating your region, determine if any logic connected to instances spanned by these nets have any timing requirements. Your region could alter the placement of all logic assigned to it. This may have an undesired side effect of altering the timing delays of some logic paths that cross through the region but are not assigned to it. These paths could fail your timing constraints depending on which net delays have been altered.

You can use one or more of the following commands or GUI tools to assign a net to a region:

• PDC - assign_net_macros
• GCF -set_net_region
• ChipPlanner - Assigning a Net to a Region

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to set the I/O supply voltage (VCCI) for I/O banks.

I/Os are organized into banks. The configuration of these banks determines the I/O standards supported. Since each I/O bank has its own user-assigned input reference voltage (VREF) and an input/output supply voltage, only I/Os with compatible standards can be assigned to the same bank.

For IGLOO, ProASIC3E, SmartFusion, Fusion and Axcelerator families, you can use the set_iobank PDC command to set the input/output supply voltage and the input reference voltage for an I/O bank. However, for ProASIC3 devices, you can use this command to set only the input/output supply voltage for an I/O bank.

For Axcelerator families, you can also use the set_iobank command to set the input delay value and enable or disable the low-power mode for input and output buffers.

You can use one or more of the following commands or GUI tools to configure I/O banks:

• PDC - set_iobank
• ChipPlanner - Manually Assigning Technologies to I/O Banks

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to create either a rectangular or rectilinear region on a device.

You can create a region within a device for setting specific physical constraints or for achieving better floorplanning. You can define regions with the array coordinates for that particular device.

For IGLOO, ProASIC3, SmartFusion, Fusion and Axcelerator families, you can use the define_region PDC command to create a rectangular or rectilinear region, and then use the assign_region PDC command to constrain a set of macros to that region.

For ProASIC PLUS and ProASIC, you can use the set_location GCF command to both create a region and constrain a set of macros to it at the same time. To define a region with the set_location command in a GCF file, you must specify the array coordinates for a rectangular area, for example, x1, y1, x2, y2.

You can also use the MultiView Navigator tool to create regions for any of the supported families.

You can use one or more of the following commands or GUI tools to create a region constraint:

• PDC -define_region
• GCF -set_location
• ChipPlanner - Creating_regions

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to remove the region(s) that you specify. You can use wildcards in the undefine_region PDC command to delete all user regions.

You can use one or more of the following commands or GUI tools to delete all regions:

• PDC - undefine_region or reset_floorplan
• ChipPlanner - Editing Regions

The following table shows which families support this constraint and which tools you can use to enter or modify it:

Use this constraint to move a Designer block from its original, locked placement by preserving the relative placement between the instances. You can move the block to the left, right, up, or down.

You can use the following command to move a Designer block:

• PDC - move_block

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to move the location of a previously defined region.

You can use one or more of the following commands or GUI tools to move a region:

• PDC - move_region
• ChipPlanner - Editing Regions

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to reserve pins for use in a later design.

You can use one or more of the following commands or GUI tools to reserve one or more pins in your design:

• PDC - reserve
• PinEditor (MVN) - Reserving pins
• I/O Attribute Editor (MVN)- Assigning pins in Package Pins View

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to either reset an I/O to its default settings or to unassign an I/O.

Attributes for an I/O, such as I/O standard, I/O threshold, Output drive, and so on, can be restored to their default values. There are no I/O banks in ProASIC PLUS or ProASIC devices; however, you can unassign I/Os in these devices using the MultiView Navigator's ChipPlanner tool.

You can use one or more of the following commands or GUI tools to restore I/O attributes:

• PDC - reset_io
• I/O Attribute Editor - Editing I/O Attributes
• ChipPlanner - Unassigning Pins

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to reset an I/O bank's technology to the default setting, which was specified in the Device Selection Wizard.

You can use one or more of the following commands or GUI tools to reset an I/O bank to its default technology:

• PDC - reset_iobank
• I/O Attribute Editor - Editing I/O Attributes
• ChipPlanner - Assigning technologies to I/O banks

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to reset a net's criticality to its default value, which is 5.

Net criticality is a guide for the place-and-route tool to keep instances connected to a net as close as possible, at the cost of other (less critical) nets. Net criticality can vary from 1 to 10 with 1 being the least critical and 10 being the most.

You can use one or more of the following commands or GUI tools to reset net criticality:

• PDC - reset_net_critical

The following table shows which families support this constraint and which tools you can use to enter or modify it:

Use this constraint to override the compile option for placement or routing conflicts for an instance of a Designer block.

You can use the following command to preserve instances:

• PDC - set_block_options

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to set the level at which the place-and-route tool must keep instances connected to a net.

Net criticality is a guide for the place-and-route tool to keep instances connected to a net as close as possible at the cost of other (less critical) nets. Net criticality can vary from 1 to 10 with 1 being the least critical and 10 being the most.

You can set a net's criticality to any number between 1 and 10 to help place-and-route tool prioritize its timing driven placement.

You can use one or more of the following commands or GUI tools to set net criticality:

• PDC - set_net_critical
• GCF - set_critical

The following table shows which families support this constraint and which tools you can use to enter or modify it:

Use this constraint to set properties on a port in the block flow.

You can use the following command to preserve instances:

• PDC - set_port_block

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to unassign a macro or a group of macros from a specific location in the device.

Macros assigned to specific locations with the set_location PDC command can be unassigned from that location using -no switch with the set_location PDC command

You can use one or more of the following commands or GUI tools to unassign a macro from a location:

• PDC - set_location and set_multitile_location
• ChipPlanner - Assigning logic to locations
• ChipEditor - Assigning Logic

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to unassign one or more macros from a specific region in the device.

Macros assigned to a specific region using the assign_region command can be unassigned from that region using the unassign_macro_from_region command

You can use one or more of the following commands or GUI tools to unassign a macro from a region:

• PDC - unassign_macro_from_region
• ChipPlanner - Unassigning a Macro from a Region

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to unassign macros that are connected to a specific net from an assigned region.

You can use one or more of the following commands or GUI tools to unassign macros on a net from a region:

• PDC - unassign_net_macros
• ChipPlanner - Unassigning a macro from a region

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Use this constraint to unreserve pins that were previously reserved. Once pins are unreserved, you can use them again in a design.

You can use one or more of the following commands or GUI tools to unreserve one or more pins in your design:

• PDC - unreserve
• PinEditor (MVN) - Reserving pins
• I/O Attribute Editor (MVN)- Assigning pins in Package Pins View