15.7.14.2 Prelayout Physical Constraint Verification

The prelayout checker performs the following DRC (Design Rule Checker) checks:

• The remaining clocks, which need to be assigned to a global clock resource, need to be less than 6. For example:

  Resource Limit
  The number of chip globals in your design exceeded the maximum number available in the device.

• The checker verifies that the total number of clock resources assigned to the given quadrant does not exceed 3. For example:

  PRL09: The number of clocks assigned (4) to the Upper Left quadrant exceeds the maximum
  number available (3) in the device.

• If a clock is placed and assigned to a quadrant clock region, the checker verifies that the clock is placed in the given quadrant clock region. For example:

  PRL11: Cannot assign net:net_out2 to the Upper Right quadrant and its driver
  macro:clkbibuf1 to Upper Left quadrant which is outside the quadrant.