24.1 Features

  • Behavior is Step Command Driven:
    • Step commands are eight bits wide
  • Commands are Stored in a Step Queue:
    • Queue depth is up to 32 entries
    • Programmable Step execution time (Step delay)
  • Supports the Command Sequence Loop:
    • Can be nested one-level deep
    • Conditional or unconditional loop
    • Two 16-bit loop counters
  • 15 Hardware Input Triggers:
    • Sensitive to either positive or negative edges, or a high or low level
  • One Software Input Trigger
  • Generates up to 32 Unique Output Trigger 
Signals
  • Generates Two Types of Trigger Outputs:
    • Individual
    • Broadcast
  • Strobed Output Port for Literal Data Values:
    • 5-bit literal write (literal part of a command)
    • 16-bit literal write (literal held in the PTGL0 register)
  • Generates up to Ten Unique Interrupt Signals
  • Two 16-Bit General Purpose Timers
  • Flexible Self-Contained Watchdog Timer (WDT) to Set an Upper Limit to Trigger Wait Time
  • Single-Step Command Capability in Debug mode
  • Selectable Clock (System, Pulse-Width Modulator (PWM) or ADC)
  • Programmable Clock Divider
Figure 24-1. PTG Block Diagram
Note:
  1. This is a dedicated Watchdog Timer for the PTG module and is independent of the device Watchdog Timer.