7.1.2 Reset Control Register
- All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset.
- If the FWDTEN Configuration bit is ‘
1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.
| Name: | RCON(1) |
| Offset: | 0xF80 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TRAPR | IOPUWR | CM | VREGS | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EXTR | SWR | SWDTEN | WDTO | SLEEP | IDLE | BOR | POR | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
Bit 15 – TRAPR Trap Reset Flag bit
| Value | Description |
|---|---|
1 |
A Trap Conflict Reset has occurred |
0 |
A Trap Conflict Reset has not occurred |
Bit 14 – IOPUWR Illegal Opcode or Uninitialized W Register Access Reset Flag bit
| Value | Description |
|---|---|
1 |
An Illegal Opcode, an Illegal Address mode or Uninitialized W Register used as an Address Pointer caused a Reset |
0 |
An Illegal Opcode or Uninitialized W Register Reset has not occurred |
Bit 9 – CM Configuration Mismatch Flag bit
| Value | Description |
|---|---|
1 |
A Configuration Mismatch Reset has occurred |
0 |
A Configuration Mismatch Reset has not occurred |
Bit 8 – VREGS Voltage Regulator Standby During Sleep bit
| Value | Description |
|---|---|
1 |
Voltage regulator is active during Sleep |
0 |
Voltage regulator goes into Standby mode during Sleep |
Bit 7 – EXTR External Reset (MCLR) Pin bit
| Value | Description |
|---|---|
1 |
A Master Clear (pin) Reset has occurred |
0 |
A Master Clear (pin) Reset has not occurred |
Bit 6 – SWR
Software RESET (Instruction) Flag bit
| Value | Description |
|---|---|
1 |
A |
0 |
A |
Bit 5 – SWDTEN Software Enable/Disable of WDT bit(2)
| Value | Description |
|---|---|
1 |
WDT is enabled |
0 |
WDT is disabled |
Bit 4 – WDTO Watchdog Timer Time-out Flag bit
| Value | Description |
|---|---|
1 |
WDT time-out has occurred |
0 |
WDT time-out has not occurred |
Bit 3 – SLEEP Wake-up from Sleep Flag bit
| Value | Description |
|---|---|
1 |
Device has been in Sleep mode |
0 |
Device has not been in Sleep mode |
Bit 2 – IDLE Wake-up from Idle Flag bit
| Value | Description |
|---|---|
1 |
Device has been in Idle mode |
0 |
Device has not been in Idle mode |
Bit 1 – BOR Brown-out Reset Flag bit
| Value | Description |
|---|---|
1 |
A Brown-out Reset has occurred |
0 |
A Brown-out Reset has not occurred |
Bit 0 – POR Power-on Reset Flag bit
| Value | Description |
|---|---|
1 |
A Power-on Reset has occurred |
0 |
A Power-on Reset has not occurred |