25.1.1 CRC Control Register Low
Legend: HC = Hardware Clearable bit, HSC = Hardware Settable/Clearable bit
| Name: | CRCCONL |
| Offset: | 0x0B0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CRCEN | CSIDL | VWORD[4:0] | |||||||
| Access | R/W | R/W | HSC/R | HSC/R | HSC/R | HSC/R | HSC/R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CRCFUL | CRCMPT | CRCISEL | CRCGO | LENDIAN | MOD | ||||
| Access | HSC/R | HSC/R | R/W | HC/R/W | R/W | R/W | |||
| Reset | 0 | 1 | 0 | 0 | 0 | 0 |
Bit 15 – CRCEN CRC Enable bit
| Value | Description |
|---|---|
| 1 | Enables module |
| 0 | Disables module |
Bit 13 – CSIDL CRC Stop in Idle Mode bit
| Value | Description |
|---|---|
| 1 | Discontinues module operation when device enters Idle mode |
| 0 | Continues module operation in Idle mode |
Bits 12:8 – VWORD[4:0] Pointer Value bits
Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN[4:0] ≥ 7 or 16 when PLEN[4:0] ≤ 7.
Bit 7 – CRCFUL CRC FIFO Full bit
| Value | Description |
|---|---|
| 1 | FIFO is full |
| 0 | FIFO is not full |
Bit 6 – CRCMPT CRC FIFO Empty bit
| Value | Description |
|---|---|
| 1 | FIFO is empty |
| 0 | FIFO is not empty |
Bit 5 – CRCISEL CRC Interrupt Selection bit
| Value | Description |
|---|---|
| 1 | Interrupt on FIFO is empty; the final word of data is still shifting through the CRC |
| 0 | Interrupt on shift is complete and results are ready |
Bit 4 – CRCGO CRC Start bit
| Value | Description |
|---|---|
| 1 | Starts CRC serial shifter |
| 0 | CRC serial shifter is turned off |
Bit 3 – LENDIAN Data Shift Direction Select bit
| Value | Description |
|---|---|
| 1 | Data word is shifted into the FIFO, starting with the LSb (little-endian) |
| 0 | Data word is shifted into the FIFO, starting with the MSb (big-endian) |
Bit 2 – MOD CRC Calculation Mode bit
| Value | Description |
|---|---|
| 1 | Alternate mode |
| 0 | Legacy mode bit |