35.6.8.7 Interrupt Enable Set
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTENSET |
| Offset: | 0x16 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERROR | RXBRK | CTSIC | RXS | RXC | TXC | DRE | |||
| Access | R/W/S | R/W/S | R/W/S | R/W/S | R/W/S | R/W/S | R/W/S | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ERROR Error Interrupt Enable
| Value | Description |
|---|---|
| 0 | Error interrupt disabled |
| 1 | Error interrupt enable |
Note:
- Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
- Writing ‘0x0’ to this bit has no effect.
- ERROR is the cummulation of the logical “OR” of STATUS.(COLL, ISF, BUFOVF, FERR, PERR) error events.
Bit 5 – RXBRK Receive Break Interrupt Enable
| Value | Description |
|---|---|
| 0 | Receive Break interrupt disabled |
| 1 | Receive Break interrupt enable |
Note:
- Writing '1' to this bit will set the Receive Break Interrupt Enable bit, which enables the Receive Break interrupt.
- Writing ‘0x0’ to this bit has no effect.
Bit 4 – CTSIC Clear to Send Input Change Interrupt Enable
| Value | Description |
|---|---|
| 0 | Clear-To-Send interrupt disabled |
| 1 | Clear-To-Send Input Change interrupt enable |
Note:
- Writing '1' to this bit will set the Clear to Send Input Change Interrupt Enable bit, which enables the Clear to Send Input Change interrupt.
- Writing ‘0x0’ to this bit has no effect.
Bit 3 – RXS Receive Start Interrupt Enable
| Value | Description |
|---|---|
| 0 | Receive Start interrupt disabled |
| 1 | Receive Start interrupt enable |
Note:
- Writing '1' to this bit will set the Receive Start Interrupt Enable bit, which enables the Receive Start interrupt.
- Writing ‘0x0’ to this bit has no effect.
Bit 2 – RXC Receive Complete Interrupt Enable
| Value | Description |
|---|---|
| 0 | Receive Complete interrupt disabled |
| 1 | Receive Complete interrupt enable |
Note:
- Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete interrupt.
- Writing ‘0x0’ to this bit has no effect.
Bit 1 – TXC Transmit Complete Interrupt Enable
| Value | Description |
|---|---|
| 0 | Transmit Complete interrupt disabled |
| 1 | Transmit Complete interrupt enable |
Note:
- Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete interrupt.
- Writing ‘0x0’ to this bit has no effect.
Bit 0 – DRE Data Register Empty Interrupt Enable
| Value | Description |
|---|---|
| 0 | Data Register Empty interrupt disabled |
| 1 | Data Register Empty interrupt enable |
Note:
- Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt.
- Writing ‘0x0’ to this bit has no effect.