35.6.8.3 Control C

Table 35-12. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: CTRLC
Offset: 0x08
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected

Bit 3130292827262524 
 TXTRHOLD[1:0]RXTRHOLD[1:0]FIFOEN DATA32B[1:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 2322212019181716 
  MAXITER[2:0]  DSNACKINACK 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 15141312111098 
     HDRDLY[1:0]BRKLEN[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
      GTIME[2:0] 
Access R/WR/WR/W 
Reset 000 

Bits 31:30 – TXTRHOLD[1:0] Transmit FIFO Threshold

These bits define the threshold for generating the Data Register Empty interrupt and DMA TX trigger.

ValueNameDescription
0x0DEFAULTInterrupt and DMA triggers can be generated as long as the FIFO is not full.
0x1HALFInterrupt and DMA triggers are generated when half FIFO space is free.
0x2EMPTYInterrupt and DMA triggers are generated when the FIFO is empty.
0x3-Reserved
Note: These bits are invalid if CTRLC.FIFOEN = 0.

Bits 29:28 – RXTRHOLD[1:0] Receive FIFO Threshold

These bits define the threshold for generating the RX Complete interrupt and DMA RX trigger.

ValueNameDescription
0x0DEFAULTInterrupt and DMA triggers can be generated as long as the FIFO is not full.
0x1HALFInterrupt and DMA triggers are generated when half FIFO space is free.
0x2FULLInterrupt and DMA triggers can be generated only when the FIFO is full.
0x3-Reserved
Note: These bits are invalid if CTRLC.FIFOEN = 0.

Bit 27 – FIFOEN FIFO Enable

This bit enables the FIFO operation.

ValueDescription
0x0FIFO operation is disabled
0x1FIFO operation is enabled

Bits 25:24 – DATA32B[1:0] Data 32 Bit

These bits configure 32-bit Extension for read and write transactions to the DATA register.

When disabled, access is according to CTRLB.CHSIZE.

ValueDescription
0x0DATA reads (for received data) and writes (for transmit data) according to CTRLB.CHSIZE.
0x1

DATA reads according to CTRLB.CHSIZE.

DATA writes using 32-bit Extension

0x2

DATA reads using 32-bit Extension.

DATA writes according to CTRLB.CHSIZE.

0x3DATA reads and writes using 32-bit Extension.

Bits 22:20 – MAXITER[2:0] Maximum Iterations

These bits define the maximum number of retransmit iterations in ISO-7816 mode, CTRLA.FORM = 0x7.

These bits also define the successive NACKs sent to the remote transmitter when CTRLC.DSNACK is set.

ValueDescription
0x0Reserved
0x11 maximum successive NACK
0x22 maximum successive NACKs
0x33 maximum successive NACKs
0x44 maximum successive NACKs
0x55 maximum successive NACKs
0x66 maximum successive NACKs
0x77 maximum successive NACKs
Note: This field is only valid when using ISO7816 T = 0 mode (CTRLA.FORM = 0x7 and CTRLA.CMODE = 0x1).

Bit 17 – DSNACK Disable Successive Not Acknowledge

This bit controls how many times NACK will be sent on parity error reception in ISO-7816 mode, CTRLA.FORM = 0x7.

ValueDescription
0x0NACK is sent on the shared Tx/Rx ISO line for every parity error received.
0x1Successive parity errors are counted up to the value specified in CTRLC.MAXITER. These parity errors generate a NACK on the shared Tx/Rx ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line.
Note:
  1. This bit is only valid in ISO7816 T = 0 mode, CTRLA.FORM = 0x7, and when CTRLC.INACK = 0x0. However, CTRLC.INACK = 1 takes priority over disable successive receive NACK CTRLC.DSNACK = 1.
  2. Parity error, STATUS.PERR = 0x1, will be set.

Bit 16 – INACK Inhibit Not Acknowledge

This bit controls whether a NACK is transmitted when a parity error is received.

ValueDescription
0x0NACK is transmitted when a parity error (STATUS.PERR = 0x1) is received
0x1NACK is not transmitted when a parity error (STATUS.PERR = 0x1) is received
Note: This bit is only valid in ISO7816 T = 0 mode, CTRLA.FORM = 0x7.

Bits 11:10 – HDRDLY[1:0] LIN Host Header Delay

These bits define the delay between break and sync transmission in addition to the delay between the sync and identifier (ID) fields when in LIN Host mode (CTRLA.FORM = 0x2).
ValueDescription
0x0Delay between break and sync transmission is 1 bit time. (CTRLB.LINCMD = 0x1)

Delay between break, sync and ID transmission is 1 bit time. (CTRLB.LINCMD = 0x2)

0x1Delay between break and sync transmission is 4 bit time. (CTRLB.LINCMD = 0x1)

Delay between sync and ID transmission is 4 bit time. (CTRLB.LINCMD = 0x2)

0x2Delay between break and sync transmission is 8 bit time. (CTRLB.LINCMD = 0x1)

Delay between sync and ID transmission is 4 bit time. (CTRLB.LINCMD = 0x2)

0x3Delay between break and sync transmission is 14 bit time. (CTRLB.LINCMD = 0x1)

Delay between sync and ID transmission is 4 bit time. (CTRLB.LINCMD = 0x2)

Note: This field is only valid when CTRLA.FORM = 0x2 and LIN header command (CTRLB.LINCMD = 0x1 or 0x2).

Bits 9:8 – BRKLEN[1:0] LIN Host Break Length

These bits define the length of the break field transmitted when in LIN Host mode.
ValueDescription
0x0Break field transmission is 13 bit times
0x1Break field transmission is 17 bit times.
0x2Break field transmission is 21 bit times.
0x3Break field transmission is 26 bit times.
Note: This field is only valid when CTRLA.FORM = 0x2 and LIN header command (CTRLB.LINCMD = 0x1 or 0x2).

Bits 2:0 – GTIME[2:0] Guard Time

These bits define the guard time when using RS485 mode (CTRLA.FORM = 0x0 or CTRLA.FORM = 0x1, and CTRLA.TXPO = 0x3) or ISO7816 mode (CTRLA.FORM = 0x7).

For RS485 mode, the guard time is programmable from 0-7 bit times and defines the time that the transmit enable (TE) pin remains high after the last stop bit is transmitted and there is no remaining data to be transmitted.

For ISO7816 T = 0 mode, the guard time is programmable from 2-9 bit times and defines the guard time between each transmitted byte.

ValueRS485 Bit Times

(CTRLA.FORM = 0x0,0x1 and TXPO = 0x3)

ISO 7816 Bit Times

(CTRLA.FORM = 0x7, TXPO = 0x0)

0x002
0x113
0x224
0x335
0x446
0x557
0x668
0x779