35.6.8.5 Receive Pulse Length Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | RXPL |
| Offset: | 0x0E |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXPL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – RXPL[7:0] Receive Pulse Length
When the data encoding format is set to IrDA, (CTRLB.ENC = 0x1), these bits control the minimum pulse width that is required for a pulse to be accepted by the IrDA receiver with regards to the SEper, serial engine clock period.
PULSE ≥ [(RXPL + 1) * (1 / fGCLK_SERCOMn_CORE)]
Note:
- SEper = 1 / fGCLK_SERCOMn_CORE.
- These bits are invalid if CTRLB.ENC = 0x0.