35.6.8.13 Data

Table 35-22. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: DATA
Offset: 0x28
Reset: 0x0000
Property: -

Bit 3130292827262524 
 DATA[31:24] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 DATA[23:16] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 DATA[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 DATA[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:0 – DATA[31:0] Data

Reading this register reads the received RX Data buffer and writing this register writes to the transmit TX data buffer. The status bits in the STATUS register should be read before reading the DATA value in order to get any corresponding errors or else they will be updated by the hardware to reflect the next Rx data after a read.

Reading these bits will return the contents of the RX Receive Data register. This register should only be read when the Receive Complete Interrupt Flag bit in the Interrupt Flag register (INTFLAG.RXC = 1) is set to indicate that received Rx data is ready to be read.

Writing these bits will write the Transmit Data register. This register should be written only when the Data Register Empty Interrupt Flag bit in the Interrupt Flag register (INTFLAG.DRE = 1) is set.

Note:
  1. If CTRLC.DATA32B = 0 reads and writes to this register are relative CTRLB.CHSIZE bits.
  2. If CTRLC.DATA32B = 1 reads and writes to this register are 32-bits, 4 bytes at a time if CHSIZE ≤ 8 bits.