35.6.8.10 Synchronization Busy
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | SYNCBUSY |
| Offset: | 0x1C |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LENGTH | RXERRCNT | CTRLB | ENABLE | SWRST | |||||
| Access | R/HS | R/HS | R/HS | R/HS | R/HS | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 4 – LENGTH LENGTH Synchronization Busy
Writing to the LENGTH register requires synchronization. When writing to LENGTH, SYNCBUSY.LENGTH will be set until synchronization is complete.
| Value | Description |
|---|---|
| 0x0 | LENGTH synchronization is not busy |
| 0x1 | LENGTH synchronization is busy |
- This bit is only valid if CTRLC.DATA32B = 1.
- If the LENGTH register is written to while SYNCBUSY.LENGTH is asserted, a bus error is generated.
Bit 3 – RXERRCNT Receive Error Count Synchronization Busy
The RXERRCNT register is automatically synchronized to the APB domain upon error. When returning from sleep, this bit will be set until the new value is available to be read.
| Value | Description |
|---|---|
| 0x0 | RXERRCNT synchronization is not busy |
| 0x1 | RXERRCNT synchronization is busy |
Bit 2 – CTRLB CTRLB Synchronization Busy
Writing to the CTRLB register when the SERCOM is enabled requires synchronization. When writing to CTRLB the SYNCBUSY.CTRLB bit will be set until synchronization is complete.
| Value | Description |
|---|---|
| 0x0 | CTRLB synchronization is not busy |
| 0x1 | CTRLB synchronization is busy |
Bit 1 – ENABLE SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When CTRLA.ENABLE is written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete.
| Value | Description |
|---|---|
| 0x0 | ENABLE synchronization is not busy |
| 0x1 | ENABLE synchronization is busy |
Bit 0 – SWRST Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete and the SERCOM module registers are reset.
| Value | Description |
|---|---|
| 0x0 | SWRST synchronization is not busy |
| 0x1 | SWRST synchronization is busy |