35.6.8.1 Control A

Table 35-10. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—


Bit	31	30	29	28	27	26	25	24
		DORD	CPOL	CMODE	FORM[3:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	SAMPA[1:0]		RXPO[1:0]				TXPO[1:0]
Access	R/W	R/W	R/W	R/W			R/W	R/W
Reset	0	0	0	0			0	0


Bit	15	14	13	12	11	10	9	8
	SAMPR[2:0]					RXINV	TXINV	IBON
Access	R/W	R/W	R/W			R/W	R/W	R/W
Reset	0	0	0			0	0	0


Bit	7	6	5	4	3	2	1	0
	RUNSTDBY			MODE[2:0]			ENABLE	SWRST
Access	R/W			R/W	R/W	R/W	R/W	R/W
Reset	0			0	0	0	0	0

Bit 30 – DORD Data Order

This bit selects the data order when a character is shifted out from the Data register.


Value	Description
0x0	MSB is transmitted first.
0x1	LSB is transmitted first.

Note: This bit is not synchronized.

Bit 29 – CPOL Clock Polarity

This bit selects the relationship between data output change and data input sampling in synchronous mode.


Value	TxD Change	RxD Sample
0x0	Rising XCK edge	Falling XCK edge
0x1	Falling XCK edge	Rising XCK edge

Note: This bit is not synchronized.

Bit 28 – CMODE Communication Mode

This bit selects asynchronous or synchronous communication.


Value	Description
0x0	Asynchronous communication.
0x1	Synchronous communication.

Note: This bit is not synchronized.

Bits 27:24 – FORM[3:0] Frame Format

These bits define the frame format.


Value	Description
0x0	USART frame
0x1	USART frame with parity
0x2	LIN Host – Break and sync generation. See LIN Command (CTRLB.LINCMD).
0x3	Reserved
0x4	Auto-baud (LIN Client) – break detection with fractional auto-baud.
0x5	Auto-baud – break detection with fractional auto-baud with parity
0x6	Reserved
0x7	ISO 7816 with parity, (Rx and Tx function must be mapped to same SERCOM PAD[0] )
0x8-0xF	Reserved

Note: These bits are not synchronized.

Bits 23:22 – SAMPA[1:0] Sample Adjustment

These bits define the sample adjustment.


Value	16x Over-sampling (CTRLA.SAMPR=0 or 1)	8x Over-sampling (CTRLA.SAMPR=2 or 3)
0x0	7-8-9	3-4-5
0x1	9-10-11	4-5-6
0x2	11-12-13	5-6-7
0x3	13-14-15	6-7-8

Note: These bits are not synchronized.

Bits 21:20 – RXPO[1:0] Receive Data Pinout

These bits define the receive data (RxD) pin configuration.


Value	Name	Description
0x0	PAD[0]	SERCOM PAD[0] is used for data reception
0x1	PAD[1]	SERCOM PAD[1] is used for data reception
0x2	PAD[2]	SERCOM PAD[2] is used for data reception
0x3	PAD[3]	SERCOM PAD[3] is used for data reception

Note: These bits are not synchronized.

Bits 17:16 – TXPO[1:0] Transmit Data Pinout

These bits define the transmit data “TxD, SERCOM PAD[0]”, “XCK, SERCOM PAD[1], “RTS/TE” SERCOM PAD[2] and “CTS” SERCOM PAD[3] pin configurations.


Value	TxD Pin	XCK (Synchronous Clock)	RTS (Request to send)	CTS (Clear to Send)	TE (Transmit Enable)	CTRLA.CMODE (Communication Mode)
0x0	SERCOM PAD[0]	SERCOM PAD[1]	—	—	—	1 = Synchronous HD - FORM = 0x7 FD - FORM = 0x0,0x1
0x0	SERCOM PAD[0]	—	—	—	—	0 = Asynchronous (RS-232 FD w/ No Flow Cntl)
0x1	Reserved	—	—	—	—	—
0x2	SERCOM PAD[0]	—	SERCOM PAD[2]	SERCOM PAD[3]	—	0 = Asynchronous (RS-232 FD with or without Flow Control)
0x3	SERCOM PAD[0]	SERCOM PAD[1]	—	—	SERCOM PAD[2]	0 = Asynchronous (RS-485 HD or FD w/ TE)

Note:

HD = Half Duplex, FD = Full Duplex.
These bits are not synchronized.

Bits 15:13 – SAMPR[2:0] Sample Rate

These bits select the RX data sample rate.


Value	Description
0x0	16x over-sampling using arithmetic baud rate generation.
0x1	16x over-sampling using fractional baud rate generation.
0x2	8x over-sampling using arithmetic baud rate generation.
0x3	8x over-sampling using fractional baud rate generation.
0x4	3x over-sampling using arithmetic baud rate generation.
0x5-0x7	Reserved

Note: These bits are not synchronized.

Bit 10 – RXINV Receive Data Invert

This bit controls whether the receive data (RxD) is inverted or not.


Value	Description
0x0	RxD is not inverted.
0x1	RxD is inverted.

Note:

Start, Parity, and Stop bits are unchanged. When enabled, Parity is calculated on the inverted data.
If ISO-7816 CTRLA.FORM = 0x7, RXINV = 1 required.

Bit 9 – TXINV Transmit Data Invert

This bit controls whether the transmit data (TxD) is inverted or not.


Value	Description
0x0	TxD is not inverted.
0x1	TxD is inverted.

Note:

Start, Parity and Stop bits are unchanged. When enabled, Parity is calculated on the inverted data.
If ISO-7816 CTRLA.FORM = 0x7, RXINV = 1 required.

Bit 8 – IBON Immediate Buffer Overflow Notification

This bit controls when the Buffer Overflow Status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs.


Value	Description
0x0	STATUS.BUFOVF is asserted when it occurs in the data stream.
0x1	STATUS.BUFOVF is asserted immediately upon buffer overflow.

Bit 7 – RUNSTDBY Run In Standby

This bit defines the functionality in Standby Sleep mode.


Value	External Clock	Internal Clock
0x0	External clock is disconnected when ongoing transfer is finished. All reception is dropped.	Generic clock is disabled when ongoing transfer is finished. The device will not wake up on either Receive Start or Transfer Complete interrupt unless the appropriate ONDEMAND bits are set in the clocking chain.
0x1	Wake on Receive Start or Receive Complete interrupt.	Generic clock is enabled in all sleep modes. Any interrupt can wake up the device.

Note:

CTRLB.SFDE must be set to 0x1 with the associated INTENSET.RXS and INTENSET.RCS values for CTRLA.RUNSTDBY = 0x1 setting to take effect.
This bit is not synchronized.

Bits 4:2 – MODE[2:0] Operating Mode

These bits select the USART serial communication interface of the SERCOM.


Value	Description
0x0	USART with external clock
0x1	USART with internal clock

Note: These bits are not synchronized.

Bit 1 – ENABLE Enable

This bit enables or disables the USART operation.


Value	Description
0x0	The peripheral is disabled or being disabled.
0x1	The peripheral is enabled or being enabled

Note:

Due to synchronization, there is a delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled.
The value written to CTRLA.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set.
SYNCBUSY.ENABLE is cleared when the operation is complete.
This bit is not enable-protected.

Bit 0 – SWRST Software Reset

Writing ‘0x1’ to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled.


Value	Description
0x0	There is no reset operation ongoing.
0x1	The reset operation is ongoing.

Note:

Writing ‘0x0’ to this bit has no effect.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. Users must wait for either CTRLA.SWRST or SYNCBUSY.SWRST to be cleared to indicate reset operation is complete.
This bit is not enable-protected.
Setting CTRLA.SWRST = 1 will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in a bus error. Reading any register will return the reset value of the register.