35.6.8.8 Interrupt Flag Status and Clear
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTFLAG |
| Offset: | 0x18 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERROR | RXBRK | CTSIC | RXS | RXC | TXC | DRE | |||
| Access | R/W/HS/K | R/W/HS/K | R/W/HS/K | R/W/HS/K | R/HS/HC | R/W/HS/K | R/HS/HC | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ERROR Error
This bit is set when any STATUS.(COLL, ISF, BUFOVF, FERR, and PERR) errors are detected.
| Value | Description |
|---|---|
| 0 | No error detected |
| 1 | Error detected |
- Before clearing this flag, the user must first clear the corresponding STATUS.(COLL, ISF, BUFOVF, FERR, or PERR) error flags as appropriate. In the case of STATUS.COLL = 1 the user must also re-enable the transmitter and set TXEN = 1.
- Writing '1' to this bit will clear the flag.
- Writing ‘0x0’ to this bit has no effect.
Bit 5 – RXBRK Receive Break
This flag is set when auto-baud is enabled, (CTRLA.FORM = 0x4 or 0x5), and a break 0x55 character is received.
| Value | Description |
|---|---|
| 0 | No Receive Break detected |
| 1 | Receive Break detected |
- Writing '1' to this bit will clear the flag.
- Writing ‘0x0’ to this bit has no effect.
Bit 4 – CTSIC Clear to Send Input Change
This flag is set when CTRLA.TXPO = 0x2 and a logic level change is detected on the “CTS” SERCOM PAD[3] pin.
| Value | Description |
|---|---|
| 0 | No Clear to Send Input Change detected |
| 1 | Clear to Send Input signal Change detected |
- Writing '1' to this bit will clear the flag.
- Writing ‘0x0’ to this bit has no effect.
Bit 3 – RXS Receive Start
This flag is set when a start condition is detected on the RxD line and start-of-frame detection is enabled (CTRLB.SFDE = 0x1).
| Value | Description |
|---|---|
| 0 | No Receive Start detected |
| 1 | Receive Start detected |
- Writing '1' to this bit will clear the flag.
- Writing ‘0x0’ to this bit has no effect.
Bit 2 – RXC Receive Complete
This flag is set when there is unread Rx data in the DATA register.
| Value | Description |
|---|---|
| 0 | No Receive Complete detected, (Rx DATA register empty) |
| 1 | Unread Rx DATA available |
- This flag is cleared by reading the Data register (DATA) or by disabling the receiver CTRLB.RXEN = 0.
- Writing ‘0’ or ‘1’ to this bit has no effect.
Bit 1 – TXC Transmit Complete
This flag is set when the entire frame in the Transmit Shift register has been shifted out and there is no new data in the Tx DATA register.
| Value | Description |
|---|---|
| 0 | No Transmit Complete detected (Tx Idle or Busy) |
| 1 | Transmit Complete, Tx DATA register empty |
- Writing '1' to this bit will clear the flag.
- Writing ‘0x0’ to this bit has no effect.
Bit 0 – DRE Tx Data Register Empty
This flag is set when Tx DATA is empty and ready to be written.
| Value | Description |
|---|---|
| 0 | Tx DATA register is not empty |
| 1 | Tx DATA register empty |
- This flag is cleared by writing new data to the DATA register.
- Writing ‘0’ or 1 to this bit has no effect.