35.6.8.9 Status

Table 35-18. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	ITER	TXE	COLL	ISF	CTS	BUFOVF	FERR	PERR
Access	R/W/HS/K	R/W/HS/K	R/W/HS/K	R/W/HS/K	R/HS	R/W/HS/K	R/W/HS/K	R/W/HS/K
Reset	0	0	0	0	0	0	0	0

Bit 7 – ITER Maximum Number of Repetitions Reached

This bit is set when the maximum number of NACK repetitions or retransmissions is met based on the CTRLC.MAXITER value.


Value	Description
0	Max. # of iterations not reached.
1	Max. # or iterations reached.

Note:

Writing ‘0x0’ to this bit has no effect.
This bit is cleared by writing ‘0x1’ to the bit or by disabling the receiver.
This bit is invalid if CTRLA.FORM ≠ 0x7.
This bit will also set INTFLAG.ERROR = 1. Users must take any appropriate actions then clear INTFLAG.ERROR and address and clear any STATUS (ITER, COLL, ISF, BUFOVF, FERR, PERR) bits before resuming normal application operation. The RX receiver is not disabled on this error.

Bit 6 – TXE Transmitter Empty

When CTRLA.FORM = 0x2 is set to LIN Host mode, this bit is set when any ongoing transmission is complete, and Tx DATA is empty.


Value	Description
0	LIN Host Transmission not complete, transmitter not empty.
1	LIN Host Transmission Complete, transmitter empty.

Note:

When CTRLA.FORM ≠ 0x2 not in LIN Host mode, this bit will always read back as zero.
Writing ‘0x0’ to this bit has no effect.
Writing ‘0x1’ to this bit will clear it.

Bit 5 – COLL Collision Detected

This bit is set when collision detection is enabled (CTRLB.COLDEN) and a collision is detected.


Value	Description
0x0	No collisions detected.
0x1	Collision detected.

Note: (When CTRLB.COLDEN = 1 and STATUS.COLL=1)

The current transfer in progress is aborted.
The TX transmit buffer and FIFO is flushed.
TX Transmitter is auto disabled in HDW, (CTRLB.TXEN = 0). This is done after a synchronization delay. The CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) will be set until this is complete. After disabling, the TxD pin will be tri-stated.
Collision Detected bit (STATUS.COLL) along with the Error Interrupt Flag (INTFLAG.ERROR) is set.
Transmit Complete Interrupt Flag, (INTFLAG.TXC), is set since the transmit buffer no longer contains data.
After a collision, software must manually enable the transmitter again before continuing, after assuring that the CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) is not set.
Writing ‘0x0’ to this bit has no effect.
Writing ‘0x1’ to this bit or by disabling the receiver will clear this bit.
This bit is invalid if CTRLB.COLDEN = 0.
Collision detect usage is confined to CTRLA.FORM = 0x7, ISO 7816 but is also possible for applications utilizing 2-wire RS485 half-duplex arrangements where the external RS485 transceiver Rx and Tx are enabled at the same time to form a loop back.
This bit will also set INTFLAG.ERROR = 1. Users must take any appropriate actions then clear INTFLAG.ERROR and address and clear any STATUS (ITER, COLL, ISF, BUFOVF, FERR, PERR) bits before resuming normal application operation.

Bit 4 – ISF Inconsistent Sync Field

This bit is set when the frame format is set to auto-baud (CTRLA.FORM = 0x4 or 0x5) and a sync field not equal to 0x55 is received.


Value	Description
0x0	No inconsistent sync fields.
0x1	Inconsistent sync field received.

Note:

Writing ‘0x0’ to this bit has no effect.
This bit is cleared by writing ‘0x1’ to the bit or by disabling the receiver.
This bit will also set INTFLAG.ERROR = 1. Users must take any appropriate actions then clear INTFLAG.ERROR and address and clear any STATUS (ITER, COLL, ISF, BUFOVF, FERR, PERR) bits before resuming normal application operation. The RX receiver is not disabled on this error.

Bit 3 – CTS Clear to Send

This bit indicates the current logic level of the CTS SERCOM PAD[3] pin when flow control is enabled (CTRLA.TXPO = 0x2).


Value	Description
0x0	CTS low
0x1	CTS high

Note: Writing a ‘0’ or ‘1’ to this bit will have no effect.

Bit 2 – BUFOVF Buffer Overflow

This bit is set when a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full, there is a new character waiting in the receive shift register and a new incoming start bit is detected. The incoming data will not be stored and lost when BUFOVF = 1, effectively pausing the module until software reads the RX DATA register, (therefore, FIFO if enabled).

Reading this bit before reading the Data register will indicate the error status of the next character to be read.


Value	Description
0x0	No buffer overflow
0x1	Buffer overflow (New incoming data will be lost until Rx DATA register read and error flags cleared.)

Note:

See: CTRLA.IBON Immediate Buffer Overflow Notification.
This bit is cleared by writing ‘0x1’ to the bit or by disabling the receiver, CTRLB.RXEN = 0. Disabling the receiver will flush the receive buffer, FIFO if enabled, and clear the FERR, PERR and BUFOVF bits in the STATUS register.
Writing ‘0x0’ to this bit has no effect.
This bit will also set INTFLAG.ERROR = 1. Users must take any appropriate actions then clear INTFLAG.ERROR and address and clear any STATUS (ITER, COLL, ISF, BUFOVF, FERR, PERR) bits before resuming normal application operation. The RX receiver is not disabled on this error.

Bit 1 – FERR Frame Error

This bit is set if the received character had a frame error, (i.e., when the expected first stop bit is a logic zero instead of a logic one. Reading this bit before reading the Data register will indicate the error status of the next character to be read.


Value	Description
0x0	No Frame Errors
0x1	Frame Error received

Note:

This bit is cleared by writing ‘0x1’ to the bit or by disabling the receiver CTRLB.RXEN = 0. Disabling the receiver will flush the receive buffer, FIFO if enabled, and clear the FERR, PERR and BUFOVF bits in the STATUS register.
Writing ‘0x0’ to this bit has no effect.
Reception is not paused on a frame error.
This bit will also set INTFLAG.ERROR = 1. User must take any appropriate actions then clear INTFLAG.ERROR and address and clear any STATUS (ITER, COLL, ISF, BUFOVF, FERR, PERR) bits before resuming normal application operation. The RX receiver is not disabled on this error.

Bit 0 – PERR Parity Error

This bit is set if parity checking is enabled (CTRLA.FORM is 0x1, 0x5, or 0x7), and a parity error is detected.

Reading this bit before reading the Data register will indicate the error status of the next character to be read.


Value	Description
0x0	No Parity Errors
0x1	Parity Error detected

Note:

This bit is cleared by writing ‘0x1’ to the bit or by disabling the receiver CTRLB.RXEN = 0. Disabling the receiver will flush the receive buffer, FIFO if enabled, and clear the FERR, PERR and BUFOVF bits in the STATUS register.
Writing ‘0x0’ to this bit has no effect.
This bit is only valid if CTRLA.FORM is 0x1, 0x5, or 0x7.
Reception is not paused on a parity error.
This bit will also set INTFLAG.ERROR= 1. Users must take any appropriate actions then clear INTFLAG.ERROR and address and clear any STATUS (ITER, COLL, ISF, BUFOVF, FERR, PERR) bits before resuming normal application operation. The RX receiver is not disabled on this error.