30.1 DC Characteristics

Table 30-2. dsPIC33CK256MC006 Family Operating Conditions
VDD RangeTemperature RangeMaximum CPU Clock Frequency
3.0V to 3.6V-40°C to +125°C100 MHz
Table 30-3. Thermal Operating Conditions
RatingSymbolMin.Max.Unit
Industrial Temperature Devices
Operating Junction Temperature RangeTJ-40+125°C
Operating Ambient Temperature RangeTA-40+85°C

Power Dissipation:

Internal Chip Power Dissipation:

PINT = VDD x (IDD – Σ IOH)

PDPINT + PI/OW

I/O Pin Power Dissipation:

I/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL)

Maximum Allowed Power DissipationPDMAX(TJ – TA)/θJAW
Table 30-4. Package Thermal Resistance(1)
PackageSymbolTyp.Unit
64-Pin TQFP 10x10x1.0 mmθJA45.7°C/W
48-Pin TQFP 7x7 mmθJA62.76°C/W
36-Pin UQFN 5x5 mmθJA29.2°C/W
28-Pin SSOP 5.30 mmθJA52.84°C/W
Note:
  1. Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.
Table 30-5. Operating Voltage Specifications

Operating Conditions (unless otherwise stated):

-40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param No.SymbolCharacteristicMin.Max.UnitsConditions
DC10VDDSupply Voltage3.03.6V
DC11AVDDSupply Voltage

Greater of:

VDD – 0.3

or 3.0

Lesser of:

VDD + 0.3

or 3.6

VThe difference between AVDD supply and VDD supply must not exceed ±300 mV at all times, including during device power-up.
DC16VPORVDD Start Voltage 


to Ensure Internal Power-on Reset Signal

—VSSV
DC17SVDDVDD Rise Rate


to Ensure Internal Power-on Reset Signal

0.03—V/ms0V-3V in 100 ms
BO10VBOR(1)BOR Event on VDD Transition High-to-Low2.682.99V
BO11VPORPOR Event on VDD Transition High-to-Low——VVDD (Notes 2, 3)
Note:
  1. Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC and comparators) may have degraded performance. The VBOR parameter is for design guidance only and is not tested in manufacturing.

  2. If VDD drops below the BO11 value, VDD must be brought down to 0V before ramping the device back up to the operation range.

Table 30-6. Operating Current (IDD)(2)
Parameter No.Typ.(1)Max.UnitsConditions
DC206.710.0mA-40°C3.3V10 MIPS (N = 1, N2 = 5, N3 = 2, 
M = 50, FVCO = 400 MHz, 
FPLLO = 40 MHz)
6.510.0mA+25°C
7.215.0mA+85°C
9.022.0mA+125°C
DC218.512.5mA-40°C3.3V20 MIPS (N = 1, N2 = 5, N3 = 1, 
M = 60, FVCO = 480 MHz, 
FPLLO = 280 MHz)
8.312.5mA+25°C
8.917.0mA+85°C
10.725.0mA+125°C
DC2212.518.5mA-40°C3.3V40 MIPS (N = 1, N2 = 3, N3 = 1, 
M = 60, FVCO = 480 MHz, 
FPLLO = 160 MHz)
12.318.5mA+25°C
13.120.0mA+85°C
14.528.0mA+125°C
DC2317.822.0mA-40°C3.3V70 MIPS (N = 1, N2 = 2, N3 = 1, 
M = 70, FVCO = 560 MHz, 
FPLLO = 280 MHz)
17.722.0mA+25°C
18.330.0mA+85°C
20.035.0mA+125°C
DC2422.328.0mA-40°C3.3V90 MIPS (N = 1, N2 = 2, N3 = 1, 
M = 90, FVCO = 720 MHz, 
FPLLO = 360 MHz)
22.028.0mA+25°C
23.033.0mA+85°C
23.535.0mA+125°C
DC2521.828.0mA-40°C3.3V100 MIPS (N = 1, N2 = 1, 
N3 = 1, M = 50, FVCO = 400 MHz, 
FPLLO = 400 MHz)
20.728.0mA+25°C
21.433.0mA+85°C
23.038.0mA+125°C
Note:
  1. Data in the “Typ.” column are for design guidance only and are not tested.
  2. IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. Base run current (IDD) is measured as follows:
    • Oscillator is switched to EC+PLL mode in software.
    • OSC1 pin is driven with an external 8 MHz square wave with levels from 0.3V to VDD – 0.3V.
    • OSC2 pin is configured as an I/O in the Configuration Words (OSCIOFNC (FOSC[2]) = 0).
    • FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 01).
    • Watchdog Timer is disabled (FWDT[15]) = 0 and WDTCONL[15] = 0).
    • All I/O pins (except OSC1) are configured as outputs and are driving low.
    • No peripheral modules are operating or being clocked (defined PMDx bits are all ‘1’s).
    • JTAG is disabled (JTAGEN (FICD[5]) = 0).
    • NOP instructions are executed in while(1) loop.
Table 30-7. Idle Current (IIDLE)(2)
Parameter No.Typ.(1)Max.UnitsConditions
DC305.57.5mA-40°C3.3V10 MIPS (N = 1, N2 = 5, N3 = 2,
 M = 50, FVCO = 400 MHz, 
FPLLO = 40 MHz)
5.37.5mA+25°C
5.812.5mA+85°C
7.720.0mA+125°C
DC316.19.0mA-40°C3.3V20 MIPS (N = 1, N2 = 5, N3 = 1, 
M = 50, FVCO = 400 MHz, 
FPLLO = 80 MHz)
5.89.0mA+25°C
6.515.0mA+85°C
8.220.0mA+125°C
DC327.612.0mA-40°C3.3V40 MIPS (N = 1, N2 = 3, N3 = 1, 
M = 60, FVCO = 480 MHz, 
FPLLO = 160 MHz)
7.412.0mA+25°C
8.215.0mA+85°C
9.722.0mA+125°C
DC339.715.0mA-40°C3.3V70 MIPS (N = 1, N2 = 2, N3 = 1, 
M = 70, FVCO = 660 MHz, 
FPLLO = 280 MHz)
9.515.0mA+25°C
10.520.0mA+85°C
11.825.0mA+125°C
DC3411.717.0mA-40°C3.3V90 MIPS (N = 1, N2 = 2, N3 = 1, 
M = 90, FVCO = 720 MHz, 
FPLLO = 360 MHz)
11.617.0mA+25°C
12.220.0mA+85°C
13.826.0mA+125°C
DC3510.117.0mA-40°C3.3V

100 MIPS (N = 1, N2 = 1, N3 = 1,

M = 50, FVCO = 400 MHz,

FPLLO = 400 MHz)

10.017.0mA+25°C
11.522.0mA+85°C
12.228.0mA+125°C
Note:
  1. Data in the “Typ.” column are for design guidance only and are not tested.
  2. Base Idle current (IIDLE) is measured as follows:
    • Oscillator is switched to EC+PLL mode in software.
    • OSC1 pin is driven with an external 8 MHz square wave with levels from 0.3V to VDD – 0.3V.
    • OSC2 is configured as an I/O in the Configuration Words (OSCIOFNC (FOSC[2]) = 0).
    • FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 01).
    • Watchdog Timer is disabled (FWDTEN (FWDT[15]) = 0).
    • All I/O pins (except OSC1) are configured as outputs and are driving low.
    • No peripheral modules are operating or being clocked (defined PMDx bits are all ‘1’s).
    • JTAG is disabled (JTAGEN (FICD[5]) = 0).
    • Flash in standby with NVMSIDL (NVMCON[12]) = 1.
Table 30-8. Power-Down Current (IPD)(2)
Parameter No.Typ.(1)Max.UnitsConditions
DC400.2850.7mA-40°C3.3VVREGS bit (RCON[8]) = 0,

LPWREN bit (VREGCON[15]) = 1

0.321.0mA+25°C
1.55.0mA+85°C
DC412.1—mA-40°C3.3VVREGS bit (RCON[8]) = 1,

LPWREN bit (VREGCON[15]) = 0

2.0—mA+25°C
2.5—mA+85°C
4.515.0mA+125°C(3)
Note:
  1. Data in the “Typ.” column are for design guidance only and are not tested.
  2. Base Sleep current (IPD) is measured as follows:
    • CPU core is off, the oscillator is configured in EC mode, and the External Clock is active; OSCI is driven with an external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required).
    • CLKO is configured as an I/O input pin in the Configuration Word.
    • FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 01).
    • All I/O pins are configured as output low.
    • MCLR = VDD, WDT and FSCM are disabled.
    • All peripheral modules are disabled (PMDx bits are all set).
    • The VREGS bit (RCON[8]) = 0 (i.e., core regulator is set to standby while the device is in Sleep mode).
    • JTAG is disabled.
  3. The regulators are in High-Power mode, LPWREN (VREGCON[15]) = 0.
Table 30-9. Doze Current (IDOZE)
Parameter No.Typ.(1)Doze RatioUnitsConditions
DC7014.11:2mA-40°C3.3V

70 MIPS (N = 1, N2 = 2,

N3 = 1, M = 70,

FVCO = 560 MHz,

FPLLO = 280 MHz)

10.01.128mA
14.01:2mA+25°C
9.71.128mA
14.31:2mA+85°C
9.41.128mA
16.51:2mA+125°C
12.01.128mA
DC7116.61:2mA-40°C3.3V

100 MIPS (N = 1, N2 = 1,

N3 = 1, M = 50,

FVCO = 400 MHz,

FPLLO = 400 MHz)

10.41.128mA
16.21:2mA+25°C
10.31.128mA
16.61:2mA+85°C
11.21.128mA
18.51:2mA+125°C
12.51.128mA
Note:
  1. Data in the “Typ.” column are for design guidance only and are not tested.
Table 30-10. Watchdog Timer Delta Current (ΔIWDT)(1)
Parameter No.Typ.UnitsConditions
DC611µA-40°C3.3V
2µA+25°C
4µA+85°C
11µA+125°C
Note:
  1. The ΔIWDT current is the additional current consumed when the module is enabled. This includes the LPRC/BFRC clock current. This current should be added to the base IPD current. All parameters are characterized but not tested during manufacturing.
Table 30-11. PWM Delta Current(1)
Parameter No.Typ.Max.UnitsConditions
DC1006.26.8mA-40°C3.3VPWM Output Frequency = 500 kHz,
PWM Input (FPLLO = 500 MHz),
(VCO = 1000 MHz, PLLFBD = 125)
6.16.7mA+25°C
6.27.4mA+85°C
7.08.6mA+125°C
DC1015.25.9mA-40°C3.3VPWM Output Frequency = 500 kHz,
PWM Input (FPLLO = 400 MHz),
(VCO = 400 MHz, PLLFBD = 100)
5.15.6mA+25°C
5.25.7mA+85°C
5.66.2mA+125°C
DC1022.53.8mA-40°C3.3VPWM Output Frequency = 500 kHz,
PWM Input (FPLLO = 200 MHz),
(VCO = 200 MHz, PLLFBD = 50)
2.63.8mA+25°C
2.53.8mA+85°C
2.53.8mA+125°C
DC1031.42.0mA-40°C3.3VPWM Output Frequency = 500 kHz,
PWM Input (FPLLO = 100 MHz),
(VCO = 100 MHz, PLLFBD = 25)
1.42.0mA+25°C
1.42.0mA+85°C
1.42.0mA+125°C
Note:
  1. All parameters are characterized but not tested during manufacturing.
Table 30-12. ADC Delta Current(1)
Parameter No.Typ.Max.UnitsConditions
DC1205.46.2mA-40°C3.3VTAD = 14.3 ns
 (3.5 Msps conversion rate)
5.46.2mA+25°C
5.56.2mA+85°C
5.66.3mA+125°C
Note:
  1. All parameters are characterized but not tested during manufacturing.
Table 30-13. Comparator + DAC Delta Current(1)
Parameter No.Typ.Max.UnitsConditions
DC1301.41.8mA-40°C3.3VFPLLO @ 500 MHz
1.31.6mA+25°C
1.31.6mA+85°C
1.41.8mA+125°C
Note:
  1. All parameters are characterized but not tested during manufacturing.
Table 30-14. I/O Pin Input Specifications
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param
 No.SymbolCharacteristicMin.Max.UnitsConditions
DI10VILInput Low-Level Voltage
Any I/O Pin and MCLRVSS0.2 VDDV
I/O Pins with SDAx, SCLxVSS0.3 VDDVSMBus disabled
I/O Pins with SDAx, SCLxVSS0.8VSMBus enabled
I/O Pins with SDAx, SCLxVSS0.8VSMBus 3.0 enabled
DI20VIHInput High-Level Voltage(1)
I/O Pins Not 5V Tolerant0.8 VDDVDDV
I/O Pins 5V Tolerant and MCLR0.8 VDD5.5V
I/O Pins 5V Tolerant with SDAx, SCLx0.8 VDD5.5VSMBus disabled
I/O Pins 5V Tolerant with SDAx, SCLx2.15.5VSMBus enabled
I/O Pins 5V Tolerant with SDAx, SCLx1.35VDDVSMBus 3.0 enabled
I/O Pins Not 5V Tolerant with SDAx, SCLx0.8 VDDVDDVSMBus disabled
I/O Pins Not 5V Tolerant with SDAx, SCLx2.1VDDVSMBus enabled
I/O Pins Not 5V Tolerant with SDAx, SCLx1.35VDDVSMBus 3.0 enabled
DI30ICNPUInput Current with Pull-up Resistor Enabled(2)175545µAVDD = 3.3V, VPIN = VSS
DI31ICNPDInput Current with Pull-Down Resistor Enabled(2)65360µAVDD = 3.3V, VPIN = VDD
DI50IILInput Leakage Current

I/O Pins and MCLR Pin

-700—nAVPIN = VSS
—700nAVPIN = VDD
Note:
  1. See the “Pin Diagrams” section for the 5V tolerant I/O pins.
  2. Characterized but not tested.
Table 30-15. I/O Pin Input Injection Current Specifications
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param
 No.SymCharacteristicMin.Max.UnitsConditions
DI60aIICLInput Low Injection Current0-5(1,4)mAThis parameter applies to all pins
DI60bIICHInput High Injection Current0+5(2,3,4)mAThis parameter applies to all pins, except all 5V tolerant pins.
DI60cΣLICTTotal Input Injection Current (sum of all I/O and control pins)-20(5)+20(5)mAAbsolute instantaneous sum of all ± input injection currents from all I/O pins:

Σ ( | IICL | + | IICH | ) ≤ ΣLICT

Note:
  1. VIL Source < (VSS – 0.3).
  2. VIH Source > (VDD + 0.3) for non-5V tolerant pins only.
  3. 5V tolerant pins do not have an internal high-side diode to VDD and therefore, cannot tolerate any “positive” input injection current.
  4. Injection currents can affect the ADC results.
  5. Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, is permitted in the sum.
Table 30-16. I/O Pin Output Specifications
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param.SymbolCharacteristicTyp.(1)UnitsConditions
DO10VOLSink Driver Voltage0.2VISINK = 3.0 mA, VDD = 3.3V
0.4VISINK = 6.0 mA, VDD = 3.3V
0.6VISINK = 9.0 mA, VDD = 3.3V
Sink Driver Voltage for

RB1, RC8, RC9, RD8 Pins

0.25VISINK = 6.0 mA, VDD = 3.3V
0.5VISINK = 12.0 mA, VDD = 3.3V
0.75VISINK = 18.0 mA, VDD = 3.3V
DO20VOHSource Driver Voltage3.1VISOURCE = 3.0 mA, VDD = 3.3V
2.9VISOURCE = 6.0 mA, VDD = 3.3V
2.7VISOURCE = 9.0 mA, VDD = 3.3V
Source Driver Voltage for

RB1, RC8, RC9, RD8 Pins

3.1VISOURCE = 6.0 mA, VDD = 3.3V
2.8VISOURCE = 12.0 mA, VDD = 3.3V
2.6VISOURCE = 18.0 mA, VDD = 3.3V
Note:
  1. Data in the “Typ.” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
Table 30-17. Program Flash Memory Specifications
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param
 No.SymCharacteristicMin.Max.UnitsConditions
Program Flash Memory
D130EPCell Endurance10,000—E/W
D134TRETDCharacteristic Retention20—Year
D137aTPESelf-Timed Page Erase Time—20ms
D137bTCESelf-Timed Chip Erase Time—20ms
D138aTWWSelf-Timed Double-Word Write Cycle Time—52.3µs6 bytes, data are not all ‘1’s
D138bTRWSelf-Timed Row Write Cycle Time—2.2ms384 bytes, data are not all ‘1’s