21.2.2 CLCx Control Register High
| Name: | CLCxCONH |
| Offset: | 0x0C2, 0x0CE, 0x0DA, 0x0E6 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| G4POL | G3POL | G2POL | G1POL | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – G4POL Gate 4 Polarity Control bit
| Value | Description |
|---|---|
| 1 | Channel 4 logic output is inverted when applied to the logic cell. |
| 0 | Channel 4 logic output is not inverted. |
Bit 2 – G3POL Gate 3 Polarity Control bit
| Value | Description |
|---|---|
| 1 | Channel 3 logic output is inverted when applied to the logic cell. |
| 0 | Channel 3 logic output is not inverted. |
Bit 1 – G2POL Gate 2 Polarity Control bit
| Value | Description |
|---|---|
| 1 | Channel 2 logic output is inverted when applied to the logic cell. |
| 0 | Channel 2 logic output is not inverted. |
Bit 0 – G1POL Gate 1 Polarity Control bit
| Value | Description |
|---|---|
| 1 | Channel 1 logic output is inverted when applied to the logic cell. |
| 0 | Channel 1 logic output is not inverted. |