3.4.1 Programmer’s Model

The programmer’s model for the dsPIC33CK256MC006 family is shown in Figure   1. All registers in the programmer’s model are memory-mapped and can be manipulated directly by instructions. Table 3-1 provides a description of each register.

In addition to the registers contained in the programmer’s model, the dsPIC33CK256MC006 devices include control registers for Modulo Addressing, Bit-Reversed Addressing and interrupts. These registers are described in subsequent sections of this document.

All registers associated with the programmer’s model are memory-mapped, as shown in Figure 3-2.

Table 3-1. Programmer’s Model Register Descriptions
Register(s) NameDescription
W0 through W15(1)Working Register Array
W0 through W14(1)Alternate Working Register Array 1
W0 through W14(1)Alternate Working Register Array 2
W0 through W14(1)Alternate Working Register Array 3
W0 through W14(1)Alternate Working Register Array 4
ACCA, ACCB40-bit DSP Accumulators (Additional Four Alternate Accumulators)
PC23-bit Program Counter
SRALU and DSP Engine STATUS Register
SPLIM16-bit Stack Pointer Limit Value Register
TBLPAG8-bit Table Memory Page Address Register
DSRPAG10-bit Extended Data Space (EDS) Read Page Register
RCOUNT16-bit REPEAT Loop Counter Register
DCOUNT16-bit DO Loop Counter Register
DOSTARTL(2)15-bit DO Loop Start Address Register (bit 0 = 0) (Low)
DOSTARTH(2)7-bit DO Loop Start Address Register (High)
DOENDL15-bit DO Loop End Address Register (bit 0 = 0) (Low)
DOENDH7-bit DO Loop End Address Register (High)
CORCONContains DSP Engine, DO Loop Control and Trap Status bits
Note:
  1. Memory-mapped W0 through W14 represent the values of the registers in the currently active CPU context.
  2. The DOSTARTH and DOSTARTL registers are read-only.
Figure 3-2. Programmer’s Model