9.5 Low-Power RC (LPRC) Oscillator

The dsPIC33CK256MC006 family devices contain one instance of the Low-Power RC (LPRC) Oscillator, which provides a nominal clock frequency of 32.768 kHz. The dsPIC33CK256MC006 family devices implement the LPRC function with the BFRC and post-divider to yield a 50% duty cycle output.

The LPRC is the clock source for the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM) circuits in the clock subsystem. The LPRC Oscillator is shut off in Sleep mode. The LPRC Oscillator remains enabled under these conditions:

• The FSCM is enabled.
• The WDT is enabled.
• The LPRC Oscillator is selected as the system clock.