10.4.9.1 Error Injection in Bus Targets

Many bus targets support Error Injection on read data returned from the bus target. This error injection will cause flags in the Interrupt Flag (INTFLAGS) register of the CPU to be set, which ordinarily will request action from the Error Controller and the Interrupt Controller.

Interrupt response can be prevented by writing the Global Interrupt Enable (I) bit in the Status Register (SREG) register to ‘0’, writing the Disable NMI Request (NMIDIS) bit in the Control A (CTRLA) register to ‘1’, and configuring the relevant Error Controller channels to severity NOTIFICATION.

See the ERRCTRL - Error Controller section for more information on severity levels.