10.4.9.2 Error Injection in the CPU

The CPU can inject errors in all control signals to the bus targets. This injection should be detected in the bus target and cause the corresponding interrupt flag in the bus target to be set, requesting an interrupt from the interrupt controller and, in most cases, returning a bus error response to the CPU. This bus error response will cause flags in the Interrupt Flags (INTFLAGS) register of the CPU to be set and will request action from the Error Controller and the Interrupt Controller. The Interrupt Flags (INTFLAGS) register in the bus target is connected to the Interrupt Controller as interrupts.

Interrupt response can be prevented by writing the Global Interrupt Enable (I) bit in the Status Register (SREG) register to ‘0’, writing the Disable NMI Request (NMIDIS) bit in the Control A (CTRLA) register to ‘1’, and configuring the relevant Error Controller channels to severity NOTIFICATION.

For details on the error injection connections, see the BUSMATRIX - Bus Matrix section.