33.3.1 Watchdog Timer Control Register
Legend: cfg = Configurable at Reset
Note:
- All these bits reflect the value of FWDT Configuration bits at Reset and can be set or cleared by software.
- When ON =
1, writes to the WINSIZE[1:0], RMPS[4:0], RMCLK[1:0], SMPS[4:0] and WINDIS are disabled.
| Name: | WDTCON |
| Offset: | 0x32C8 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | WINSIZE[1:0] | RMPS[4:0] | |||||||
| Access | R/W-cfg | R/W-cfg | R/W-cfg | R/W-cfg | R/W-cfg | R/W-cfg | R/W-cfg | R/W-cfg | |
| Reset | |||||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RMCLK[1:0] | SMPS[4:0] | WINDIS | |||||||
| Access | R/W-cfg | R/W-cfg | R/W-cfg | R/W-cfg | R/W-cfg | R/W-cfg | R/W-cfg | R/W-cfg | |
| Reset | |||||||||
Bit 15 – ON On bit(2)
| Value | Description |
|---|---|
| 1 | Enables the WDT. |
| 0 | Disable and reset WDT. |
Bits 14:13 – WINSIZE[1:0] Size of Watchdog Window bits
| Value | Description |
|---|---|
| 11 | Window size is 25% (Timer Count > 11xxx...xxxxx for the timer to be cleared). |
| 10 | Window size is 37.5% (Timer Count > 101xx...xxxxx for the timer to be cleared). |
| 01 | Window size is 50% (Timer Count > 1xxxx...xxxxx for the timer to be cleared). |
| 00 | Window size is 75% (Timer Count > 01xxx...xxxxx for the timer to be cleared). |
Bits 12:8 – RMPS[4:0] Configures the postscaler value for Run Mode Counter bits
Bits 7:6 – RMCLK[1:0] Watchdog Timer Run Mode Counter Clock Selection bits
| Value | Description |
|---|---|
| 11 | LPRC Oscillator |
| 10 | BFRC Oscillator |
| 01 | Reserved |
| 00 | FOSC/4 |
Bits 5:1 – SMPS[4:0] Configures the Postscaler Value for Sleep Mode Counter bits
Refer to Table 33-2 for the encoding of this bit field.
Bit 0 – WINDIS Watchdog Window Mode Disable bit
| Value | Description |
|---|---|
| 1 | Disables Window mode. |
| 0 | Enables Window mode. |