13.7.3 Peripheral Module Disable (PMD) Register

The Peripheral Module Disable (PMD) registers provide a method to disable DMA by stopping all clock sources supplied to it.

When DMA is disabled via PMD controlled bits, the DMA Controller is in a Minimum Power Consumption state. The module-level registers (DMACON, DMABUF, DMAHIGH and DMALOW) remain active. However, the control and status registers associated with any disabled channels will be disabled, so writes to those registers will have no effect and read values will be invalid.