33.4.3 Enabling and Disabling the Watchdog Timer

The Reset value of each bit in the WDTCON SFR can be determined by the FWDT configuration register to allow the WDT to be either disabled or enabled and preconfigured at device start-up.

The Watchdog Timer is enabled or disabled by the WDT ON(WDTCON[15]) bit. When the ON bit is set, the WDT is enabled and writes to the WINSIZE [1:0], RMPS [4:0], RMCLK [1:0], SMPS [4:0] and WINDIS are disabled. Additionally, writes to the WDTCON register can also be locked using PACCON2[WDWTCONWR] to avoid accidental WDT writes.

If the ON bit is cleared in the WDTCON register, the WDT is disabled and reset and WDTCON SFR modification is allowed.

The ON bit in WDTCON mirrors the ON bit in the FWDT Configuration register on device Reset. The ON bit allows the user application to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings.

The WDT flag bit, WDTO (RCON[4]), is not cleared automatically after a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software.

Note: The Run mode WDT is expected to stall when the device is performing any Flash operation while executing the code from the same Flash partition, and it is expected to resume its Run mode counter once the Flash operation is complete.