22.5.1.3 Host Input Compensation

The host input compensation delay (I2CxHIDLYC ) is used for feedback input delay compensation. The feedback path delay is expected within the calculated BRG time-out, but the estimated path delay may go slightly higher due to system-dependent parameters (external voltage and pull-up resistance connected) to the SCK and SDA. When the feedback path delay is greater than the calculated BRG time-out, the BRG time-out expiration must be extended using the programmable delay compensation.

Equation 22-2. HDLYC Calculation
HIDLYCVALUE[15:0] = [(Fi2c/(2 * FSCL) – BRG[23:0] * 1/Fi2c] +2
Note:
  1. The I2CxHIDLYC is most useful to delay compensation for 1 MHz I2C clock.
  2. Due to system-dependent parameters, the actual delay may differ slightly with respect to BRG. Testing is required to confirm that the actual delay values meets the system requirements. Otherwise, the value of the HIDLYC register may need to be adjusted.