29.2.1 CRC Control Register

Legend: R = Readable bit, W = Writable bit

Name:	CRCCON
Offset:	0x2C8


Bit	31	30	29	28	27	26	25	24
				DWIDTH[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
				PLEN[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ON		SIDL	VWORD[4:0]
Access	R/W		R/W	R	R	R	R	R
Reset	0		0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CRCFULL	CRCEMPTY	CRCISEL	CRCGO	LENDIAN	MOD
Access	R	R	R/W	R/W	R/W	R/W
Reset	0	1	0	0	0	0

Bits 28:24 – DWIDTH[4:0] Data Word Width Configuration bits

Configures the width of the data word (data word width - 1).

Bits 20:16 – PLEN[4:0] Polynomial Length Configuration bits

Configures the length of the polynomial (polynomial length - 1),

Bit 15 – ON CRC Enable bit

Value	Description
`1`	Enables module.
`0`	Disables module. All state machines, pointers and CRCSHFT/CRCDAT reset. Other SFRs are not reset.

Bit 13 – SIDL CRC Stop in Idle Mode bit

Value	Description
`1`	Discontinue the module operation when the device enters Idle mode.
`0`	Continue the module operation in Idle mode.

Bits 12:8 – VWORD[4:0] Valid Word Pointer Value bits

Indicates the number of valid words in the FIFO,

Has a maximum value of 16 when DWIDTH[4:0] ≦ 7 (data words 8-bit wide or less).
Has a maximum value of 8 when DWIDTH[4:0] ≦ 15 (data words from 9-bit to 16-bit wide).
Has a maximum value of 4 when DWIDTH[4:0] ≦ 31 (data words from 17-bit to 32-bit wide).

Bit 7 – CRCFULL FIFO Full bit

Value	Description
`1`	FIFO is full.
`0`	FIFO is not full.

Bit 6 – CRCEMPTY FIFO Empty bit

Value	Description
`1`	FIFO empty
`0`	FIFO not empty

Bit 5 – CRCISEL CRC Interrupt Selection bit

Value	Description
`1`	Interrupt on FIFO empty; final word of data still shifting through CRC.
`0`	Interrupt on shift complete and results ready.

Bit 4 – CRCGO Start CRC bit

Value	Description
`1`	Start CRC serial shifter; clearing the bit aborts shifting.
`0`	CRC serial shifter turned off.

Bit 3 – LENDIAN Little Endian Enable bit

Value	Description
`1`	Data word is shifted into the CRC starting with the LSb (little endian).
`0`	Data word is shifted into the CRC starting with the MSb (big endian).

Bit 2 – MOD Accumulator Mode bit

Value	Description
`1`	Accumulator configured for x¹⁶ + x¹² + x⁵ + 1 (when MOD = `1`)
`0`	Accumulator configured for x¹⁶ + x¹² + x⁵ + 1 (when MOD = `0`)

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