41.7.3 CSI Main Interrupt Status
Register
The following configuration values are valid for all listed bit names of this
register:
0: No event occurred since the last read of the register.
1: An event occurred since the last read of the register.
| Name: | CSI_INT_ST_MAIN |
| Offset: | 0xC |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | STATUS_INT_PKT | STATUS_INT_PHY | |
| Access | | | | | | | R | R | |
| Reset | | | | | | | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | STATUS_INT_FRAME_FATAL | STATUS_INT_PKT_FATAL | STATUS_INT_PHY_FATAL | |
| Access | | | | | | R | R | R | |
| Reset | | | | | | 0 | 0 | 0 | |
Bit 17 – STATUS_INT_PKT CSI_INT_ST_PKT Register
Event (cleared on read)
Indicates if an event occurred
in the CSI_INT_ST_PKT register.
Bit 16 – STATUS_INT_PHY CSI_INT_ST_PHY Register
Event (cleared on read)
Indicates if an event occurred
in the CSI_INT_ST_PHY register.
Bit 2 – STATUS_INT_FRAME_FATAL CSI_INT_ST_FRAME_FATAL
Register Event (cleared on read)
Indicates if an event occurred
in the CSI_INT_ST_FRAME_FATAL register.
Bit 1 – STATUS_INT_PKT_FATAL CSI_INT_ST_PKT_FATAL
Register Event (cleared on Read)
Indicates if an event occurred
in the CSI_INT_ST_PKT_FATAL register.
Bit 0 – STATUS_INT_PHY_FATAL CSI_INT_ST_PHY_FATAL
Register Event (cleared on read)
Indicates if an event occurred
in the CSI_INT_ST_PHY_FATAL register.
