41.7.17 CSI Frame Error Interrupt Status Register
Interrupt sources related to Frame construction. Packet discarded.
Reading CSI_INT_ST_FRAME_FATAL does not clear the interrupt pin.
The following configuration values are valid for all listed bit names of this register:
0: No event occurred since the last read of the register.
1: An event occurred since the last read of the register.
Name: | CSI_INT_ST_FRAME_FATAL |
Offset: | 0x100 |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
ERR_FRAME_DATA_VC3 | ERR_FRAME_DATA_VC2 | ERR_FRAME_DATA_VC1 | ERR_FRAME_DATA_VC0 | ||||||
Access | R | R | R | R | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
ERR_F_SEQ_VC3 | ERR_F_SEQ_VC2 | ERR_F_SEQ_VC1 | ERR_F_SEQ_VC0 | ||||||
Access | R | R | R | R | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ERR_F_BNDRY_MATCH_VC3 | ERR_F_BNDRY_MATCH_VC2 | ERR_F_BNDRY_MATCH_VC1 | ERR_F_BNDRY_MATCH_VC0 | ||||||
Access | R | R | R | R | |||||
Reset | 0 | 0 | 0 | 0 |