41.7.23 CSI Packet Interrupt Status Register

Reading CSI_INT_ST_PKT does not clear the interrupt pin.

The following configuration values are valid for all listed bit names of this register:

0: No event occurred since the last read of the register.

1: An event occurred since the last read of the register.

Name: CSI_INT_ST_PKT
Offset: 0x120
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     VC3_ERR_ECC_CORRECTEDVC2_ERR_ECC_CORRECTEDVC1_ERR_ECC_CORRECTEDVC0_ERR_ECC_CORRECTED 
Access RRRR 
Reset 0000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     ERR_ID_VC3ERR_ID_VC2ERR_ID_VC1ERR_ID_VC0 
Access RRRR 
Reset 0000 

Bit 19 – VC3_ERR_ECC_CORRECTED Header Error Detected and Corrected on Virtual Channel 3 (cleared on read)

Bit 18 – VC2_ERR_ECC_CORRECTED Header Error Detected and Corrected on Virtual Channel 2 (cleared on read)

Bit 17 – VC1_ERR_ECC_CORRECTED Header Error Detected and Corrected on Virtual Channel 1 (cleared on read)

Bit 16 – VC0_ERR_ECC_CORRECTED Header Error Detected and Corrected on Virtual Channel 0 (cleared on read)

Bit 3 – ERR_ID_VC3 Unrecognized or Unimplemented Data Type Detected in Virtual Channel 3 (cleared on read)

Bit 2 – ERR_ID_VC2 Unrecognized or Unimplemented Data Type Detected in Virtual Channel 2 (cleared on read)

Bit 1 – ERR_ID_VC1 Unrecognized or Unimplemented Data Type Detected in Virtual Channel 1 (cleared on read)

Bit 0 – ERR_ID_VC0 Unrecognized or Unimplemented Data Type Detected in Virtual Channel 0 (cleared on read)