41.7.8 CSI D-PHY Analog Configuration Control Register

Name: CSI_PHY_TEST_CTRL0
Offset: 0x50
Reset: 0x00000001
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
       PHY_TESTCLKPHY_TESTCLR 
Access R/WR/W 
Reset 01 

Bit 1 – PHY_TESTCLK Analog Configuration Control Clock

The data is loaded on one edge of PHY_TESTCLK, thus it is mandatory to write a '0' immediately after writing a '1'. Refer to PHY_TEST_CTRL1.PHY_TESTDEN.
ValueDescription
0

No effect.
1

Captures the PHY_TEST_CTRL1.PHY_TESTDIN value.

Bit 0 – PHY_TESTCLR Analog Configuration Clear

The reset is performed on the rising edge of PHY_TESTCLR, thus it is mandatory to write a '0' immediately after writing a '1'.
ValueDescription
0

No effect.
1

Resets the analog configuration.