41.7.9 CSI D-PHY Analog Configuration Data Register
| Name: | CSI_PHY_TEST_CTRL1 |
| Offset: | 0x54 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PHY_TESTEN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PHY_TESTDOUT[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PHY_TESTDIN[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 16 – PHY_TESTEN Analog Configuration Code Selection
| Value | Description |
|---|---|
| 0 |
Transmits the high-speed bit rate code on the rising edge of CSI_PHY_TEST_CTRL0.PHY_TESTCLK. |
| 1 |
Transmits the address (0x44) of the high-speed bit rate code on the falling edge of CSI_PHY_TEST_CTRL0.PHY_TESTCLK. |