41.7.7 CSI D-PHY Stop State Register
| Name: | CSI_PHY_STOPSTATE |
| Offset: | 0x4C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PHY_STOPSTATECLK | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PHY_STOPSTATEDATA_1 | PHY_STOPSTATEDATA_0 | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bit 16 – PHY_STOPSTATECLK Clock Lane Stop State Status
| Value | Description |
|---|---|
| 0 | Clock lane module is not in Stop state. |
| 1 | Clock lane module is in Stop state. |
Bit 1 – PHY_STOPSTATEDATA_1 Data Lane 1 Stop State Status
| Value | Description |
|---|---|
| 0 | Data lane 1 module is not in Stop state. |
| 1 | Data lane 1 module has entered Stop state. |
Bit 0 – PHY_STOPSTATEDATA_0 Data Lane 0 Stop State Status
| Value | Description |
|---|---|
| 0 | Data lane 0 module is not in Stop state. |
| 1 | Data lane 0 module has entered Stop state. |